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/linux/Documentation/arch/riscv/
H A Dcmodx.rst32 According to Ziccif, as long as an instruction is naturally aligned, the ISA
H A Dhwprobe.rst413 * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported,
/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml563 - const: ziccif
565 The standard Ziccif extension for main memory (cacheability and
/linux/arch/riscv/kernel/
H A Dsys_hwprobe.c207 EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing); in hwprobe_isa_ext1()
H A Dcpufeature.c529 __RISCV_ISA_EXT_DATA(ziccif, RISCV_ISA_EXT_ZICCIF),