xref: /linux/Documentation/devicetree/bindings/net/mscc,miim.yaml (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mscc,miim.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microsemi MII Management Controller (MIIM)
8
9maintainers:
10  - Alexandre Belloni <alexandre.belloni@bootlin.com>
11
12allOf:
13  - $ref: mdio.yaml#
14
15properties:
16  compatible:
17    enum:
18      - mscc,ocelot-miim
19      - microchip,lan966x-miim
20
21  "#address-cells":
22    const: 1
23
24  "#size-cells":
25    const: 0
26
27  reg:
28    items:
29      - description: base address
30      - description: associated reset register for internal PHYs
31    minItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  clocks:
37    maxItems: 1
38
39  clock-frequency: true
40
41  resets:
42    items:
43      - description:
44          Reset shared with all blocks attached to the Switch Core Register
45          Bus (CSR) including VRAP slave.
46
47  reset-names:
48    items:
49      - const: switch
50
51required:
52  - compatible
53  - reg
54  - "#address-cells"
55  - "#size-cells"
56
57unevaluatedProperties: false
58
59examples:
60  - |
61    mdio@107009c {
62      compatible = "mscc,ocelot-miim";
63      reg = <0x107009c 0x36>, <0x10700f0 0x8>;
64      interrupts = <14>;
65      #address-cells = <1>;
66      #size-cells = <0>;
67
68      phy0: ethernet-phy@0 {
69        reg = <0>;
70      };
71    };
72