| /linux/drivers/media/platform/mediatek/vpu/ |
| H A D | mtk_vpu.c | 23 * VPU (video processor unit) is a tiny processor controlling video hardware
25 * VPU interfaces with other blocks by share memory and interrupt.
44 /* the size of share buffer between Host and VPU */
68 /* vpu inter-processor communication interrupt */
70 /* vpu idle state */
74 * enum vpu_fw_type - VPU firmware type
86 * struct vpu_mem - VPU extended program/data memory information
88 * @va: the kernel virtual memory address of VPU extended memory
89 * @pa: the physical memory address of VPU extended memory
98 * struct vpu_regs - VPU TCM and configuration registers
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| H A D | mtk_vpu.h | 13 * DOC: VPU
15 * VPU (video processor unit) is a tiny processor controlling video hardware
17 * VPU interfaces with other blocks by share memory and interrupt.
27 * @IPI_VPU_INIT: The interrupt from vpu is to notfiy kernel
28 * VPU initialization completed.
29 * IPI_VPU_INIT is sent from VPU when firmware is
31 * command to VPU.
33 * to VPU to trigger the interrupt.
34 * @IPI_VDEC_H264: The interrupt from vpu is to notify kernel to
42 * @IPI_VDEC_VP9: The interrupt from vpu is to notify kernel to
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| /linux/drivers/media/platform/mediatek/mdp3/ |
| H A D | mtk-mdp3-vpu.c | 9 #include "mtk-mdp3-vpu.h"
14 static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu) in vpu_to_mdp() argument
16 return container_of(vpu, struct mdp_dev, vpu); in vpu_to_mdp()
19 static int mdp_vpu_shared_mem_alloc(struct mdp_vpu_dev *vpu) in mdp_vpu_shared_mem_alloc() argument
23 if (IS_ERR_OR_NULL(vpu)) in mdp_vpu_shared_mem_alloc()
26 dev = scp_get_device(vpu->scp); in mdp_vpu_shared_mem_alloc()
28 if (!vpu->param) { in mdp_vpu_shared_mem_alloc()
29 vpu->param = dma_alloc_wc(dev, vpu->param_size, in mdp_vpu_shared_mem_alloc()
30 &vpu->param_addr, GFP_KERNEL); in mdp_vpu_shared_mem_alloc()
31 if (!vpu->param) in mdp_vpu_shared_mem_alloc()
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| /linux/drivers/media/platform/amphion/ |
| H A D | vpu_drv.c | 26 #include "vpu.h"
32 void vpu_writel(struct vpu_dev *vpu, u32 reg, u32 val) in vpu_writel() argument
34 writel(val, vpu->base + reg); in vpu_writel()
37 u32 vpu_readl(struct vpu_dev *vpu, u32 reg) in vpu_readl() argument
39 return readl(vpu->base + reg); in vpu_readl()
42 static void vpu_dev_get(struct vpu_dev *vpu) in vpu_dev_get() argument
44 if (atomic_inc_return(&vpu->ref_vpu) == 1 && vpu->res->setup) in vpu_dev_get()
45 vpu->res->setup(vpu); in vpu_dev_get()
48 static void vpu_dev_put(struct vpu_dev *vpu) in vpu_dev_put() argument
50 atomic_dec(&vpu->ref_vpu); in vpu_dev_put()
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| H A D | vpu_imx8q.c | 15 #include "vpu.h"
42 int vpu_imx8q_setup_dec(struct vpu_dev *vpu) in vpu_imx8q_setup_dec() argument
46 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f); in vpu_imx8q_setup_dec()
47 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff); in vpu_imx8q_setup_dec()
52 int vpu_imx8q_setup_enc(struct vpu_dev *vpu) in vpu_imx8q_setup_enc() argument
57 int vpu_imx8q_setup(struct vpu_dev *vpu) in vpu_imx8q_setup() argument
61 vpu_readl(vpu, offset + 0x108); in vpu_imx8q_setup()
63 vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1); in vpu_imx8q_setup()
64 vpu_writel(vpu, offset + 0x190, 0xffffffff); in vpu_imx8q_setup()
65 vpu_writel(vpu, offset + SCB_BLK_CTRL_XMEM_RESET_SET, 0xffffffff); in vpu_imx8q_setup()
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| H A D | vpu_core.c | 21 #include "vpu.h"
180 vpu_trace(core->dev, "vpu core state change from %d to %d\n", core->state, state); in vpu_core_set_state()
199 static struct vpu_core *vpu_core_find_proper_by_type(struct vpu_dev *vpu, u32 type) in vpu_core_find_proper_by_type() argument
205 list_for_each_entry(c, &vpu->cores, list) { in vpu_core_find_proper_by_type()
229 static bool vpu_core_is_exist(struct vpu_dev *vpu, struct vpu_core *core) in vpu_core_is_exist() argument
233 list_for_each_entry(c, &vpu->cores, list) { in vpu_core_is_exist()
243 core->vpu->get_vpu(core->vpu); in vpu_core_get_vpu()
245 core->vpu->get_enc(core->vpu); in vpu_core_get_vpu()
247 core->vpu->get_dec(core->vpu); in vpu_core_get_vpu()
252 struct vpu_dev *vpu = dev_get_drvdata(dev); in vpu_core_register() local
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| /linux/drivers/media/platform/mediatek/vcodec/decoder/ |
| H A D | vdec_vpu_if.c | 14 struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *) in handle_init_ack_msg() local
17 mtk_vdec_debug(vpu->ctx, "+ ap_inst_addr = 0x%llx", msg->ap_inst_addr); in handle_init_ack_msg()
19 /* mapping VPU address to kernel virtual address */ in handle_init_ack_msg()
20 /* the content in vsi is initialized to 0 in VPU */ in handle_init_ack_msg()
21 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_init_ack_msg()
23 vpu->inst_addr = msg->vpu_inst_addr; in handle_init_ack_msg()
25 mtk_vdec_debug(vpu->ctx, "- vpu_inst_addr = 0x%x", vpu->inst_addr); in handle_init_ack_msg()
28 vpu->fw_abi_version = 0; in handle_init_ack_msg()
33 vpu->inst_id = 0xdeadbeef; in handle_init_ack_msg()
35 /* VPU firmware does not contain a version field. */ in handle_init_ack_msg()
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| H A D | vdec_vpu_if.h | 13 * struct vdec_vpu_inst - VPU instance for video codec
16 * @vsi : driver structure allocated by VPU side and shared to AP side
18 * @failure : VPU execution result status, 0: success, others: fail
19 * @inst_addr : VPU decoder instance address
23 * @signaled : 1 - Host has received ack message from VPU, 0 - not received
25 * @wq : wait queue to wait VPU message ack
49 * vpu_dec_init - init decoder instance and allocate required resource in VPU.
51 * @vpu: instance for vdec_vpu_inst
53 int vpu_dec_init(struct vdec_vpu_inst *vpu);
59 * @vpu : instance for vdec_vpu_inst
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| /linux/drivers/media/platform/mediatek/vcodec/encoder/ |
| H A D | venc_vpu_if.c | 11 static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *data) in handle_enc_init_msg() argument
15 vpu->inst_addr = msg->vpu_inst_addr; in handle_enc_init_msg()
16 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_enc_init_msg()
20 if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) == VPU) in handle_enc_init_msg()
24 mtk_venc_debug(vpu->ctx, "firmware version: 0x%x\n", msg->venc_abi_version); in handle_enc_init_msg()
29 mtk_venc_err(vpu->ctx, "unhandled firmware version 0x%x\n", in handle_enc_init_msg()
31 vpu->failure = 1; in handle_enc_init_msg()
36 static void handle_enc_encode_msg(struct venc_vpu_inst *vpu, const void *data) in handle_enc_encode_msg() argument
40 vpu->state = msg->state; in handle_enc_encode_msg()
41 vpu->bs_size = msg->bs_size; in handle_enc_encode_msg()
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| H A D | venc_ipi_msg.h | 16 * enum venc_ipi_msg_id - message id between AP and VPU
18 * @AP_IPIMSG_ENC_XXX: AP to VPU cmd message id
19 * @VPU_IPIMSG_ENC_XXX_DONE: VPU ack AP cmd message id
34 * struct venc_ap_ipi_msg_init - AP to VPU init cmd structure
36 * @reserved: reserved for future use. vpu is running in 32bit. Without
38 * will be different between kernel and vpu
49 * struct venc_ap_ipi_msg_set_param - AP to VPU set_param cmd structure
51 * @vpu_inst_addr: VPU encoder instance addr
71 * struct venc_ap_ipi_msg_enc - AP to VPU enc cmd structure
73 * @vpu_inst_addr: VPU encoder instance addr
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| H A D | venc_vpu_if.h | 13 * struct venc_vpu_inst - encoder VPU driver instance
14 * @wq_hd: wait queue used for vpu cmd trigger then wait vpu interrupt done
15 * @signaled: flag used for checking vpu interrupt done
16 * @failure: flag to show vpu cmd succeeds or not
20 * @inst_addr: VPU instance addr
21 * @vsi: driver structure allocated by VPU side and shared to AP side for
40 int vpu_enc_init(struct venc_vpu_inst *vpu);
41 int vpu_enc_set_param(struct venc_vpu_inst *vpu,
44 int vpu_enc_encode(struct venc_vpu_inst *vpu, unsigned int bs_mode,
48 int vpu_enc_deinit(struct venc_vpu_inst *vpu);
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| /linux/drivers/media/platform/mediatek/mdp/ |
| H A D | mtk_mdp_vpu.c | 13 static inline struct mtk_mdp_ctx *vpu_to_ctx(struct mtk_mdp_vpu *vpu) in vpu_to_ctx() argument
15 return container_of(vpu, struct mtk_mdp_ctx, vpu); in vpu_to_ctx()
20 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_handle_init_ack() local
23 /* mapping VPU address to kernel virtual address */ in mtk_mdp_vpu_handle_init_ack()
24 vpu->vsi = (struct mdp_process_vsi *) in mtk_mdp_vpu_handle_init_ack()
25 vpu_mapping_dm_addr(vpu->pdev, msg->vpu_inst_addr); in mtk_mdp_vpu_handle_init_ack()
26 vpu->inst_addr = msg->vpu_inst_addr; in mtk_mdp_vpu_handle_init_ack()
34 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_ipi_handler() local
38 vpu->failure = msg->status; in mtk_mdp_vpu_ipi_handler()
39 if (!vpu->failure) { in mtk_mdp_vpu_ipi_handler()
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| /linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu2_hw_jpeg_enc.c | 3 * Hantro VPU codec driver
9 * The VPU JPEG encoder produces JPEG baseline sequential format.
35 static void rockchip_vpu2_set_src_img_ctrl(struct hantro_dev *vpu, in rockchip_vpu2_set_src_img_ctrl() argument
51 vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); in rockchip_vpu2_set_src_img_ctrl()
61 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET); in rockchip_vpu2_set_src_img_ctrl()
64 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); in rockchip_vpu2_set_src_img_ctrl()
67 static void rockchip_vpu2_jpeg_enc_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_jpeg_enc_set_buffers() argument
82 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(dst_buf, 0) + in rockchip_vpu2_jpeg_enc_set_buffers()
85 vepu_write_relaxed(vpu, size_left, VEPU_REG_STR_BUF_LIMIT); in rockchip_vpu2_jpeg_enc_set_buffers()
89 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); in rockchip_vpu2_jpeg_enc_set_buffers()
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| H A D | hantro_h1_jpeg_enc.c | 3 * Hantro VPU codec driver
18 static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu, in hantro_h1_set_src_img_ctrl() argument
37 vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL); in hantro_h1_set_src_img_ctrl()
40 static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu, in hantro_h1_jpeg_enc_set_buffers() argument
55 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(dst_buf, 0) + in hantro_h1_jpeg_enc_set_buffers()
58 vepu_write_relaxed(vpu, size_left, H1_REG_STR_BUF_LIMIT); in hantro_h1_jpeg_enc_set_buffers()
63 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
67 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
68 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1); in hantro_h1_jpeg_enc_set_buffers()
73 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
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| H A D | imx8m_vpu_hw.c | 3 * Hantro VPU codec driver
28 static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) in imx8m_soft_reset() argument
33 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
35 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
40 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
42 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
45 static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) in imx8m_clk_enable() argument
49 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
51 writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
54 static int imx8mq_runtime_resume(struct hantro_dev *vpu) in imx8mq_runtime_resume() argument
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| H A D | rockchip_vpu2_hw_vp8_dec.c | 3 * Rockchip VPU codec vp8 decode driver
280 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
285 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
291 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
295 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
302 vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ); in cfg_lf()
306 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
308 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
319 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
323 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
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| H A D | hantro_g1_h264_dec.c | 3 * Rockchip RK3288 VPU codec driver
28 struct hantro_dev *vpu = ctx->dev; in set_params() local
49 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in set_params()
55 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in set_params()
65 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in set_params()
71 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); in set_params()
85 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); in set_params()
100 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5); in set_params()
107 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6); in set_params()
110 vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); in set_params()
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| H A D | rockchip_vpu2_hw_mpeg2_dec.c | 3 * Hantro VPU codec driver
83 rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_quantisation() argument
90 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE); in rockchip_vpu2_mpeg2_dec_set_quantisation()
94 rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_buffers() argument
114 vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
122 vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
139 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
140 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
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| H A D | hantro_g1_vp8_dec.c | 139 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
144 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
150 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
154 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
161 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); in cfg_lf()
165 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
167 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
181 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
185 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
191 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); in cfg_qp()
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| H A D | hantro.h | 3 * Hantro VPU codec driver
56 * struct hantro_variant - information about VPU hardware variant
58 * @enc_offset: Offset from VPU base to encoder registers.
59 * @dec_offset: Offset from VPU base to decoder registers.
93 int (*init)(struct hantro_dev *vpu);
94 int (*runtime_resume)(struct hantro_dev *vpu);
139 * struct hantro_func - Hantro VPU functionality
180 * @pdev: Pointer to VPU platform device.
185 * @reg_bases: Mapped addresses of VPU registers.
186 * @enc_base: Mapped address of VPU encoder register for convenience.
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| H A D | hantro_g1_mpeg2_dec.c | 3 * Hantro VPU codec driver
81 hantro_g1_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in hantro_g1_mpeg2_dec_set_quantisation() argument
88 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, G1_REG_QTABLE_BASE); in hantro_g1_mpeg2_dec_set_quantisation()
92 hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx, in hantro_g1_mpeg2_dec_set_buffers() argument
111 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); in hantro_g1_mpeg2_dec_set_buffers()
119 vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE); in hantro_g1_mpeg2_dec_set_buffers()
133 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
134 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
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| H A D | hantro_g1.c | 3 * Hantro VPU codec driver
16 struct hantro_dev *vpu = dev_id; in hantro_g1_irq() local
20 status = vdpu_read(vpu, G1_REG_INTERRUPT); in hantro_g1_irq()
24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
27 hantro_irq_done(vpu, state); in hantro_g1_irq()
34 struct hantro_dev *vpu = ctx->dev; in hantro_g1_reset() local
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
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| H A D | rockchip_vpu2_hw_h264_dec.c | 3 * Hantro VPU codec driver
199 struct hantro_dev *vpu = ctx->dev; in set_params() local
207 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in set_params()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in set_params()
216 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in set_params()
219 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in set_params()
227 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in set_params()
233 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in set_params()
248 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); in set_params()
253 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59)); in set_params()
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | amphion,vpu.yaml | 5 $id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
8 title: Amphion VPU codec IP
20 pattern: "^vpu@[0-9a-f]+$"
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
45 Each vpu encoder or decoder correspond a MU, which used for communication
50 "^vpu-core@[0-9a-f]+$":
61 - nxp,imx8q-vpu-decoder
62 - nxp,imx8q-vpu-encoder
114 vpu: vpu@2c000000 {
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| /linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/ |
| H A D | vdec_vp9_if.c | 30 * struct vp9_dram_buf - contains buffer info for vpu
46 * @reserved : reserved field used by vpu
68 * @reserved : reserved field used by vpu
89 * struct vdec_vp9_vsi - shared buffer between host and VPU firmware
91 * VPU-W/R: VPU is write/reader on this item
92 * @sf_bs_buf : super frame backup buffer (AP-W, VPU-R)
94 * (AP-R/W, VPU-R/W)
95 * @sf_next_ref_fb_idx : next available super frame (AP-W, VPU-R)
96 * @sf_frm_cnt : super frame count, filled by vpu (AP-R, VPU-W)
97 * @sf_frm_offset : super frame offset, filled by vpu (AP-R, VPU-W)
[all …]
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