Searched full:vhdl (Results 1 – 10 of 10) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/input/ |
| H A D | ps2keyb-mouse-apbps2.txt | 3 The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library.
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-grgpio.txt | 3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
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| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | grcan.txt | 3 The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | ste-coh901318.txt | 4 ARM PL08x PrimeCell VHDL code.
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | gr-udc.txt | 3 The GRUSBDC USB Device Controller core is available in the GRLIB VHDL
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | arm,pl18x.yaml | 16 vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
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| /freebsd/contrib/bearssl/ |
| H A D | Doxyfile | 261 # Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
262 # sources. Doxygen will then generate output that is tailored for VHDL.
275 # or free formatted code, this is the default for Fortran type files), VHDL. For
797 # *.vhd, *.vhdl, *.ucf, *.qsf, *.as and *.js.
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| /freebsd/contrib/libcbor/ |
| H A D | Doxyfile | 301 # Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
302 # sources. Doxygen will then generate output that is tailored for VHDL.
321 # VHDL, Fortran (fixed format Fortran: FortranFixed, free formatted Fortran:
950 # *.vhdl, *.ucf, *.qsf and *.ice.
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| /freebsd/contrib/ldns/ |
| H A D | libdns.doxygen.in | 286 # Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
287 # sources. Doxygen will then generate output that is tailored for VHDL.
305 # Csharp (C#), C, C++, D, PHP, md (Markdown), Objective-C, Python, Slice, VHDL,
888 # *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, *.f18, *.f, *.for, *.vhd, *.vhdl,
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| /freebsd/contrib/unbound/doc/ |
| H A D | unbound.doxygen | 300 # Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
301 # sources. Doxygen will then generate output that is tailored for VHDL.
320 # VHDL, Fortran (fixed format Fortran: FortranFixed, free formatted Fortran:
974 # *.vhdl, *.ucf, *.qsf and *.ice.
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