xref: /linux/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml (revision 4db102dcb0396a4ccf89b1eac0f4eb3fd167a080) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI 7nm PHY
8
9maintainers:
10  - Jonathan Marek <jonathan@marek.ca>
11
12allOf:
13  - $ref: dsi-phy-common.yaml#
14
15properties:
16  compatible:
17    enum:
18      - qcom,dsi-phy-7nm
19      - qcom,dsi-phy-7nm-8150
20      - qcom,sc7280-dsi-phy-7nm
21      - qcom,sm6375-dsi-phy-7nm
22      - qcom,sm8350-dsi-phy-5nm
23      - qcom,sm8450-dsi-phy-5nm
24      - qcom,sm8550-dsi-phy-4nm
25      - qcom,sm8650-dsi-phy-4nm
26
27  reg:
28    items:
29      - description: dsi phy register set
30      - description: dsi phy lane register set
31      - description: dsi pll register set
32
33  reg-names:
34    items:
35      - const: dsi_phy
36      - const: dsi_phy_lane
37      - const: dsi_pll
38
39  vdds-supply:
40    description: |
41      Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
42
43  phy-type:
44    description: D-PHY (default) or C-PHY mode
45    enum: [ 10, 11 ]
46    default: 10
47
48required:
49  - compatible
50  - reg
51  - reg-names
52
53unevaluatedProperties: false
54
55examples:
56  - |
57     #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
58     #include <dt-bindings/clock/qcom,rpmh.h>
59
60     dsi-phy@ae94400 {
61         compatible = "qcom,dsi-phy-7nm";
62         reg = <0x0ae94400 0x200>,
63               <0x0ae94600 0x280>,
64               <0x0ae94900 0x260>;
65         reg-names = "dsi_phy",
66                     "dsi_phy_lane",
67                     "dsi_pll";
68
69         #clock-cells = <1>;
70         #phy-cells = <0>;
71
72         vdds-supply = <&vreg_l5a_0p88>;
73         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
74                  <&rpmhcc RPMH_CXO_CLK>;
75         clock-names = "iface", "ref";
76     };
77