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/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2055.h95 #define B2055_VCO_CAL1 0x40 /* VCO cal 1 */
96 #define B2055_VCO_CAL2 0x41 /* VCO cal 2 */
97 #define B2055_VCO_CAL3 0x42 /* VCO cal 3 */
98 #define B2055_VCO_CAL4 0x43 /* VCO cal 4 */
99 #define B2055_VCO_CAL5 0x44 /* VCO cal 5 */
100 #define B2055_VCO_CAL6 0x45 /* VCO cal 6 */
101 #define B2055_VCO_CAL7 0x46 /* VCO cal 7 */
102 #define B2055_VCO_CAL8 0x47 /* VCO cal 8 */
103 #define B2055_VCO_CAL9 0x48 /* VCO cal 9 */
104 #define B2055_VCO_CAL10 0x49 /* VCO cal 10 */
[all …]
/freebsd/sys/dev/qcom_clk/
H A Dqcom_clk_fepll.c73 uint64_t vco, parent_rate; in qcom_clk_fepll_recalc() local
96 vco = parent_rate / refclkdiv; in qcom_clk_fepll_recalc()
97 vco = vco * 2; in qcom_clk_fepll_recalc()
98 vco = vco * fdbkdiv; in qcom_clk_fepll_recalc()
100 *freq = vco; in qcom_clk_fepll_recalc()
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dfsl,plldig.yaml30 fsl,vco-hz:
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
35 its own desired VCO frequency for the PLL.
H A Darm,syscon-icst.yaml74 description: The VCO register
77 description: Parent clock for the ICST VCO
87 vco-offset:
89 description: Offset to the VCO register for the oscillator
105 vco-offset = <0x00>;
H A Dqcom,dispcc-sc8280xp.yaml31 - description: DisplayPort 0 VCO div clock
33 - description: DisplayPort 1 VCO div clock
35 - description: DisplayPort 2 VCO div clock
37 - description: DisplayPort 3 VCO div clock
H A Dqcom,sm8450-dispcc.yaml35 - description: VCO DIV clock from DP PHY0
37 - description: VCO DIV clock from DP PHY1
39 - description: VCO DIV clock from DP PHY2
41 - description: VCO DIV clock from DP PHY3
H A Dqcom,dispcc-sm8x50.yaml38 - description: VCO DIV clock from DP PHY
40 - description: VCO DIV clock from eDP PHY
42 - description: VCO DIV clock from DP1 PHY
44 - description: VCO DIV clock from DP2 PHY
H A Dqcom,sm8550-dispcc.yaml40 - description: VCO DIV clock from DP PHY0
42 - description: VCO DIV clock from DP PHY1
44 - description: VCO DIV clock from DP PHY2
46 - description: VCO DIV clock from DP PHY3
H A Dqcom,mmcc.yaml151 - description: eDP phy PLL vco clock
190 - description: eDP phy PLL vco clock
299 - description: DisplayPort phy PLL vco clock
335 - description: DisplayPort phy PLL vco clock
H A Dti,lmk04832.yaml60 ti,vco-hz:
61 description: Optional to set VCO frequency of the PLL in Hertz.
183 ti,vco-hz = <2457600000>;
H A Dqcom,sc7280-dispcc.yaml29 - description: VCO DIV clock from DP PHY
31 - description: VCO DIV clock from EDP PHY
H A Dst,stm32-rcc.txt81 6 PLL_VCO_I2S (vco frequency of I2S pll)
82 7 PLL_VCO_SAI (vco frequency of SAI pll)
H A Dbaikal,bt1-ccu-pll.yaml59 CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
71 divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
/freebsd/sys/arm/mv/armadaxp/
H A Darmadaxp.c88 uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
89 uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */
90 uint8_t vco_hcl; /* VCO to HCLK(DDR controller) clock ratio */
91 uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-eb.dtsi237 vco-offset = <0x0C>;
245 vco-offset = <0x10>;
253 vco-offset = <0x14>;
261 vco-offset = <0x18>;
269 vco-offset = <0x1c>;
H A Darm-realview-pb11mp.dts346 vco-offset = <0x0C>;
354 vco-offset = <0x10>;
362 vco-offset = <0x14>;
370 vco-offset = <0x18>;
378 vco-offset = <0x1c>;
386 vco-offset = <0xd4>;
394 vco-offset = <0xd8>;
H A Dintegratorap.dts88 vco-offset = <0x08>;
98 vco-offset = <0x1c>;
119 vco-offset = <0x04>;
129 vco-offset = <0x04>;
H A Darm-realview-pbx.dtsi259 vco-offset = <0x0C>;
267 vco-offset = <0x10>;
275 vco-offset = <0x14>;
283 vco-offset = <0x18>;
291 vco-offset = <0x1c>;
H A Darm-realview-pb1176.dts263 vco-offset = <0x0C>;
271 vco-offset = <0x10>;
279 vco-offset = <0x14>;
287 vco-offset = <0x18>;
295 vco-offset = <0x1c>;
H A Dintegratorcp.dts100 vco-offset = <0x08>;
110 vco-offset = <0x08>;
120 vco-offset = <0x1c>;
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c72 #define PLL_FLAG_VCO_OUT 0x02 /* Output VCO directly */
355 * VCO is directly exposed as pllP_out0, P div is used for
1030 uint64_t vco, pfd; in plld2_set_freq() local
1044 vco = *fout * p; in plld2_set_freq()
1045 if (vco < PLLD2_VCO_MIN) in plld2_set_freq()
1047 if (vco > PLLD2_VCO_MAX) in plld2_set_freq()
1058 vco = (fin * n) / m; in plld2_set_freq()
1059 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN) in plld2_set_freq()
1062 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN) in plld2_set_freq()
1066 err = *fout - vco / p; in plld2_set_freq()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadi,adf4377.yaml7 title: ADF4377 Microwave Wideband Synthesizer with Integrated VCO
15 phased locked loop (PLL) with integrated voltage controlled oscillator (VCO)
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c807 uint64_t vco, pfd; in plld2_set_freq() local
821 vco = *fout * p; in plld2_set_freq()
822 if (vco < PLLD2_VCO_MIN) in plld2_set_freq()
824 if (vco > PLLD2_VCO_MAX) in plld2_set_freq()
835 vco = (fin * n) / m; in plld2_set_freq()
836 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN) in plld2_set_freq()
839 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN) in plld2_set_freq()
843 err = *fout - vco / p; in plld2_set_freq()
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra234-clock.h202 /** @brief PLLP vco output */
452 /** @brief PLLC4 VCO followed by DIV3 path */
454 /** @brief PLLC4 VCO followed by DIV5 path */
458 /** @brief PLLC4 VCO followed by DIV2 path */
816 /** @brief DSIPLL VCO output */
822 /** @brief SPPLL0 VCO output */
836 /** @brief SPPLL1 VCO output */
/freebsd/sys/dev/e1000/
H A De1000_82540.c455 * Set the output amplitude to the value in the EEPROM and adjust the VCO
479 /* Adjust VCO speed to improve BER performance */ in e1000_setup_fiber_serdes_link_82540()
524 * e1000_set_vco_speed_82540 - Set VCO speed for better performance
527 * Set the VCO speed to improve Bit Error Rate (BER) performance.

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