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/freebsd/sys/contrib/device-tree/Bindings/soc/renesas/
H A Drenesas,r9a09g011-sys.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g011-sys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2M System Configuration (SYS)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The RZ/V2M-alike SYS (System Configuration) controls the overall
15 - Bank address settings for DMAC
16 - Bank address settings of the units for ICB
17 - ETHER AxCACHE[1] (C bit) control function
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Drenesas,rzg2l-cpg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
14 Standby Mode share the same register block. On RZ/V2M, the functionality is
18 - The CPG block generates various core clocks,
19 - The Module Standby Mode block provides two functions:
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