Home
last modified time | relevance | path

Searched +full:v1 +full:- +full:v6 (Results 1 – 25 of 93) sorted by relevance

1234

/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h34 * eg. aud110->base.ctx
37 * eg. aud110->regs->reg
67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument
69 FN(reg, f1), v1,\
72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
74 FN(reg, f1), v1,\
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
80 FN(reg, f1), v1,\
85 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
88 FN(reg, f1), v1,\
[all …]
/linux/arch/powerpc/crypto/
H A Dcrc32-vpmsum_core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * 32 bits of 0s to the end - this matches what a CRC does. We just
28 #include <asm/ppc-opcode.h>
66 std r31,-8(r1)
67 std r30,-16(r1)
68 std r29,-24(r1)
69 std r28,-32(r1)
70 std r27,-40(r1)
71 std r26,-48(r1)
72 std r25,-56(r1)
[all …]
/linux/arch/arm64/crypto/
H A Dsm4-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
35 ld1 {v16.16b-v19.16b}, [x5], #64; \
36 ld1 {v20.16b-v23.16b}, [x5], #64; \
37 ld1 {v24.16b-v27.16b}, [x5], #64; \
38 ld1 {v28.16b-v31.16b}, [x5];
103 /* sbox, non-linear part */ \
105 tbl RTMP0.16b, {v16.16b-v19.16b}, RX0.16b; \
107 tbx RTMP0.16b, {v20.16b-v23.16b}, RX0.16b; \
109 tbx RTMP0.16b, {v24.16b-v27.16b}, RX0.16b; \
[all …]
H A Daes-neonbs-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
14 * for 32-bit ARM written by Andy Polyakov <appro@openssl.org>
216 ldp q18, q19, [bskey, #-96]
217 ldp q20, q21, [bskey, #-64]
218 ldp q22, q23, [bskey, #-32]
222 ldp q16, q17, [bskey, #-128]!
406 cmtst v1.16b, v7.16b, v9.16b
411 cmtst v6.16b, v7.16b, v14.16b
414 not v1.16b, v1.16b
[all …]
H A Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
66 st1 {v0.16b-v3.16b}, [x0], #64
[all …]
H A Dsm4-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
45 * x0: 128-bit key
53 ld1 {v1.16b}, [x3];
55 ld1 {v24.16b-v27.16b}, [x4], #64;
56 ld1 {v28.16b-v31.16b}, [x4];
59 eor v0.16b, v0.16b, v1.16b;
62 sm4ekey v1.4s, v0.4s, v25.4s;
[all …]
H A Dchacha-neon-core.S4 * Copyright (C) 2016-2018 Linaro, Ltd. <ard.biesheuvel@linaro.org>
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
29 * chacha_permute - permute one block
31 * Permute one 64-byte block where the state matrix is stored in the four NEON
32 * registers v0-v3. It performs matrix operations on four words in parallel,
46 add v0.4s, v0.4s, v1.4s
52 eor v4.16b, v1.16b, v2.16b
53 shl v1.4s, v4.4s, #12
54 sri v1.4s, v4.4s, #20
57 add v0.4s, v0.4s, v1.4s
[all …]
H A Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
59 ld1 {v25.8b-v28.8b}, [x1], #32
60 ld1 {v29.8b-v31.8b}, [x1], #24
[all …]
H A Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd.
15 .arch armv8-a+crypto
20 ld1 {v10.4s-v13.4s}, [\rk]
21 ld1 {v14.4s-v17.4s}, [\tmp], #64
22 ld1 {v18.4s-v21.4s}, [\tmp], #64
23 ld1 {v3.4s-v5.4s}, [\tmp]
55 ld1 {v1.8b}, [x6] /* load upper ctr */
59 ins v1.d[1], x9 /* no carry in lower ctr */
[all …]
H A Dsm3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sm3-ce-core.S - SM3 secure hash using ARMv8.2 Crypto Extensions
55 ext v6.16b, \s0\().16b, \s1\().16b, #12
68 sm3partw2 \s4\().4s, v7.4s, v6.4s
79 ld1 {v8.4s-v9.4s}, [x0]
89 0: ld1 {v0.16b-v3.16b}, [x1], #64
96 CPU_LE( rev32 v1.16b, v1.16b )
102 qround a, v0, v1, v2, v3, v4
103 qround a, v1, v2, v3, v4, v0
104 qround a, v2, v3, v4, v0, v1
[all …]
/linux/drivers/char/mwave/
H A Dmwavedd.h3 * mwavedd.h -- declarations for mwave device driver
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 * 10/23/2000 - Alpha Release
79 #define PRINTK_2(f,s,v1) \ argument
81 printk(s,v1); \
84 #define PRINTK_3(f,s,v1,v2) \ argument
86 printk(s,v1,v2); \
89 #define PRINTK_4(f,s,v1,v2,v3) \ argument
91 printk(s,v1,v2,v3); \
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
31 #include "atom-bits.h"
42 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_overscan_setup()
51 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_overscan_setup()
53 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
61 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in amdgpu_atombios_crtc_overscan_setup()
[all …]
H A Datombios_encoders.c2 * Copyright 2007-11 Advanced Micro Devices, Inc.
74 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_get_backlight_level()
77 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_get_backlight_level()
87 struct drm_encoder *encoder = &amdgpu_encoder->base; in amdgpu_atombios_encoder_set_backlight_level()
88 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_set_backlight_level()
92 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_set_backlight_level()
95 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && in amdgpu_atombios_encoder_set_backlight_level()
96 amdgpu_encoder->enc_priv) { in amdgpu_atombios_encoder_set_backlight_level()
97 dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_encoder_set_backlight_level()
98 dig->backlight_level = level; in amdgpu_atombios_encoder_set_backlight_level()
[all …]
/linux/arch/riscv/crypto/
H A Dchacha-riscv64-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
39 // The generated code of this file depends on the following RISC-V extensions:
40 // - RV64I
41 // - RISC-V Vector ('V') with VLEN >= 128
42 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
87 vror.vi \d0, \d0, 32 - 16
88 vror.vi \d1, \d1, 32 - 16
89 vror.vi \d2, \d2, 32 - 16
90 vror.vi \d3, \d3, 32 - 16
[all …]
H A Daes-macros.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
41 // This file contains macros that are shared by the other aes-*.S files. The
42 // generated code of these macros depends on the following RISC-V extensions:
43 // - RV64I
44 // - RISC-V Vector ('V') with VLEN >= 128
45 // - RISC-V Vector AES block cipher extension ('Zvkned')
49 // - If AES-128, loads round keys into v1-v11 and jumps to \label128.
50 // - If AES-192, loads round keys into v1-v13 and jumps to \label192.
51 // - If AES-256, loads round keys into v1-v15 and continues onwards.
[all …]
/linux/lib/
H A Dtest_dynamic_debug.c1 // SPDX-License-Identifier: GPL-2.0-only
34 * - classmaps must have corresponding enum
35 * - enum symbols must match/correlate with class-name strings in the map.
36 * - base must equal enum's 1st value
37 * - multiple maps must set their base to share the 0-30 class_id space !!
38 * (build-bug-on tips welcome)
40 * - tie together sysname, mapname, bitsname, flagsname
84 /* numeric verbosity, V2 > V1 related */
85 enum cat_level_num { V0 = 14, V1, V2, V3, V4, V5, V6, V7 }; enumerator
87 "V0", "V1", "V2", "V3", "V4", "V5", "V6", "V7");
[all …]
/linux/arch/powerpc/lib/
H A Dmemcpy_power7.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
40 clrldi r6,r6,(64-3)
65 stdu r1,-STACKFRAMESIZE(r1)
119 clrldi r5,r5,(64-7)
178 9: clrldi r5,r5,(64-4)
207 15: ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
217 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
218 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
220 stdu r1,-STACKFRAMESIZE(r1)
[all …]
H A Dcopyuser_power7.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
69 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
70 ld r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
71 ld r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
79 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
80 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
81 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
96 clrldi r6,r6,(64-3)
121 stdu r1,-STACKFRAMESIZE(r1)
175 clrldi r5,r5,(64-7)
[all …]
H A Dmemcmp_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/ppc-opcode.h>
42 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1); \
43 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1); \
44 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
46 stdu r1,-STACKFRAMESIZE(r1); \
58 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1); \
59 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1); \
60 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
62 stdu r1,-STACKFRAMESIZE(r1); \
[all …]
/linux/tools/testing/selftests/powerpc/copyloops/
H A Dmemcpy_power7.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
40 clrldi r6,r6,(64-3)
65 stdu r1,-STACKFRAMESIZE(r1)
119 clrldi r5,r5,(64-7)
178 9: clrldi r5,r5,(64-4)
207 15: ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
217 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
218 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
220 stdu r1,-STACKFRAMESIZE(r1)
[all …]
H A Dcopyuser_power7.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
69 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
70 ld r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
71 ld r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
79 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
80 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
81 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
96 clrldi r6,r6,(64-3)
121 stdu r1,-STACKFRAMESIZE(r1)
175 clrldi r5,r5,(64-7)
[all …]
/linux/tools/testing/selftests/powerpc/stringloops/
H A Dmemcmp_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/ppc-opcode.h>
42 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1); \
43 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1); \
44 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
46 stdu r1,-STACKFRAMESIZE(r1); \
58 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1); \
59 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1); \
60 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
62 stdu r1,-STACKFRAMESIZE(r1); \
[all …]
/linux/Documentation/ABI/testing/
H A Dconfigfs-tsm3 KernelVersion: v6.7
4 Contact: linux-coco@lists.linux.dev
12 KernelVersion: v6.7
13 Contact: linux-coco@lists.linux.dev
22 KernelVersion: v6.7
23 Contact: linux-coco@lists.linux.dev
30 "cert_table" from SEV-ES Guest-Hypervisor Communication Block
32 https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/specifications/56421.pdf
36 KernelVersion: v6.10
37 Contact: linux-coco@lists.linux.dev
[all …]
/linux/drivers/ufs/host/
H A Dufs-mediatek-sip.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * Multi-VCC by Numbering
46 unsigned long v1; member
51 unsigned long v6; member
60 s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res); in _ufs_mtk_smc()
/linux/drivers/gpu/drm/radeon/
H A Datombios_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
42 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
43 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
[all …]

1234