1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7988-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek MT7988 Pin Controller 8 9maintainers: 10 - Sean Wang <sean.wang@kernel.org> 11 12description: 13 The MediaTek's MT7988 Pin controller is used to control SoC pins. 14 15properties: 16 compatible: 17 enum: 18 - mediatek,mt7988-pinctrl 19 20 reg: 21 minItems: 7 22 maxItems: 7 23 24 reg-names: 25 items: 26 - const: gpio 27 - const: iocfg_tr 28 - const: iocfg_br 29 - const: iocfg_rb 30 - const: iocfg_lb 31 - const: iocfg_tl 32 - const: eint 33 34 gpio-controller: true 35 36 "#gpio-cells": 37 const: 2 38 39 gpio-ranges: 40 minItems: 1 41 maxItems: 5 42 description: 43 GPIO valid number range. 44 45 interrupt-controller: true 46 47 interrupts: 48 maxItems: 1 49 50 "#interrupt-cells": 51 const: 2 52 53allOf: 54 - $ref: pinctrl.yaml# 55 56required: 57 - compatible 58 - reg 59 - reg-names 60 - gpio-controller 61 - "#gpio-cells" 62 63patternProperties: 64 '-pins$': 65 type: object 66 additionalProperties: false 67 68 properties: 69 mux: 70 type: object 71 additionalProperties: false 72 $ref: /schemas/pinctrl/pinmux-node.yaml 73 description: | 74 pinmux configuration nodes. 75 76 The following table shows the effective values of "group", "function" 77 properties and chip pinout pins 78 79 groups function pins (in pin#) 80 --------------------------------------------------------------------- 81 "tops_jtag0_0" "jtag" 0, 1, 2, 3, 4 82 "wo0_jtag" "jtag" 50, 51, 52, 53, 54 83 "wo1_jtag" "jtag" 50, 51, 52, 53, 54 84 "wo2_jtag" "jtag" 50, 51, 52, 53, 54 85 "jtag" "jtag" 58, 59, 60, 61, 62 86 "tops_jtag0_1" "jtag" 58, 59, 60, 61, 62 87 "int_usxgmii" "int_usxgmii" 2, 3 88 "pwm0" "pwm" 57 89 "pwm1" "pwm" 21 90 "pwm2" "pwm" 80 91 "pwm2_0" "pwm" 58 92 "pwm3" "pwm" 81 93 "pwm3_0" "pwm" 59 94 "pwm4" "pwm" 82 95 "pwm4_0" "pwm" 60 96 "pwm5" "pwm" 83 97 "pwm5_0" "pwm" 61 98 "pwm6" "pwm" 69 99 "pwm6_0" "pwm" 62 100 "pwm7" "pwm" 70 101 "pwm7_0" "pwm" 4 102 "dfd" "dfd" 0, 1, 2, 3, 4 103 "xfi_phy0_i2c0" "i2c" 0, 1 104 "xfi_phy1_i2c0" "i2c" 0, 1 105 "xfi_phy_pll_i2c0" "i2c" 3, 4 106 "xfi_phy_pll_i2c1" "i2c" 3, 4 107 "i2c0_0" "i2c" 5, 6 108 "i2c1_sfp" "i2c" 5, 6 109 "xfi_pextp_phy0_i2c" "i2c" 5, 6 110 "xfi_pextp_phy1_i2c" "i2c" 5, 6 111 "i2c0_1" "i2c" 15, 16 112 "u30_phy_i2c0" "i2c" 15, 16 113 "u32_phy_i2c0" "i2c" 15, 16 114 "xfi_phy0_i2c1" "i2c" 15, 16 115 "xfi_phy1_i2c1" "i2c" 15, 16 116 "xfi_phy_pll_i2c2" "i2c" 15, 16 117 "i2c1_0" "i2c" 17, 18 118 "u30_phy_i2c1" "i2c" 17, 18 119 "u32_phy_i2c1" "i2c" 17, 18 120 "xfi_phy_pll_i2c3" "i2c" 17, 18 121 "sgmii0_i2c" "i2c" 17, 18 122 "sgmii1_i2c" "i2c" 17, 18 123 "i2c1_2" "i2c" 69, 70 124 "i2c2_0" "i2c" 69, 70 125 "i2c2_1" "i2c" 71, 72 126 "mdc_mdio0" "eth" 5, 6 127 "2p5g_ext_mdio" "eth" 28, 29 128 "gbe_ext_mdio" "eth" 30, 31 129 "mdc_mdio1" "eth" 69, 70 130 "pcie_wake_n0_0" "pcie" 7 131 "pcie_clk_req_n0_0" "pcie" 8 132 "pcie_wake_n3_0" "pcie" 9 133 "pcie_clk_req_n3" "pcie" 10 134 "pcie_clk_req_n0_1" "pcie" 10 135 "pcie_p0_phy_i2c" "pcie" 7, 8 136 "pcie_p1_phy_i2c" "pcie" 7, 8 137 "pcie_p3_phy_i2c" "pcie" 9, 10 138 "pcie_p2_phy_i2c" "pcie" 7, 8 139 "ckm_phy_i2c" "pcie" 9, 10 140 "pcie_wake_n0_1" "pcie" 13 141 "pcie_wake_n3_1" "pcie" 14 142 "pcie_2l_0_pereset" "pcie" 19 143 "pcie_1l_1_pereset" "pcie" 20 144 "pcie_clk_req_n2_1" "pcie" 63 145 "pcie_2l_1_pereset" "pcie" 73 146 "pcie_1l_0_pereset" "pcie" 74 147 "pcie_wake_n1_0" "pcie" 75 148 "pcie_clk_req_n1" "pcie" 76 149 "pcie_wake_n2_0" "pcie" 77 150 "pcie_clk_req_n2_0" "pcie" 78 151 "pcie_wake_n2_1" "pcie" 79 152 "pmic" "pmic" 11 153 "watchdog" "watchdog" 12 154 "spi0_wp_hold" "spi" 22, 23 155 "spi0" "spi" 24, 25, 26, 27 156 "spi1" "spi" 28, 29, 30, 31 157 "spi2" "spi" 32, 33, 34, 35 158 "spi2_wp_hold" "spi" 36, 37 159 "snfi" "flash" 22, 23, 24, 25, 26, 27 160 "emmc_45" "flash" 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 161 "sdcard" "flash" 32, 33, 34, 35, 36, 37 162 "emmc_51" "flash" 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 163 "uart2" "uart" 0, 1, 2, 3 164 "tops_uart0_0" "uart" 22, 23 165 "uart2_0" "uart" 28, 29, 30, 31 166 "uart1_0" "uart" 32, 33, 34, 35 167 "uart2_1" "uart" 32, 33, 34, 35 168 "net_wo0_uart_txd_0" "uart" 28 169 "net_wo1_uart_txd_0" "uart" 29 170 "net_wo2_uart_txd_0" "uart" 30 171 "tops_uart1_0" "uart" 28, 29 172 "tops_uart0_1" "uart" 30, 31 173 "tops_uart1_1" "uart" 36, 37 174 "uart0" "uart" 55, 56 175 "tops_uart0_2" "uart" 55, 56 176 "uart2_2" "uart" 50, 51, 52, 53 177 "uart1_1" "uart" 58, 59, 60, 61 178 "uart2_3" "uart" 58, 59, 60, 61 179 "uart1_2" "uart" 80, 81, 82, 83 180 "uart1_2_lite" "uart" 80, 81 181 "tops_uart1_2" "uart" 80, 81 182 "net_wo0_uart_txd_1" "uart" 80 183 "net_wo1_uart_txd_1" "uart" 81 184 "net_wo2_uart_txd_1" "uart" 82 185 "udi" "udi" 32, 33, 34, 35, 36 186 "i2s" "audio" 50, 51, 52, 53, 54 187 "pcm" "audio" 50, 51, 52, 53 188 "gbe0_led1" "led" 58 189 "gbe1_led1" "led" 59 190 "gbe2_led1" "led" 60 191 "gbe3_led1" "led" 61 192 "2p5gbe_led1" "led" 62 193 "gbe0_led0" "led" 64 194 "gbe1_led0" "led" 65 195 "gbe2_led0" "led" 66 196 "gbe3_led0" "led" 67 197 "2p5gbe_led0" "led" 68 198 "drv_vbus_p1" "usb" 63 199 "drv_vbus" "usb" 79 200 201 properties: 202 function: 203 description: 204 A string containing the name of the function to mux to the group. 205 enum: [audio, dfd, eth, flash, i2c, int_usxgmii, jtag, led, pcie, pmic, pwm, spi, 206 uart, udi, usb, watchdog] 207 groups: 208 description: 209 An array of strings. Each string contains the name of a group. 210 211 required: 212 - function 213 - groups 214 215 allOf: 216 - if: 217 properties: 218 function: 219 const: audio 220 then: 221 properties: 222 groups: 223 enum: [i2s, pcm] 224 - if: 225 properties: 226 function: 227 const: jtag 228 then: 229 properties: 230 groups: 231 enum: [jtag, tops_jtag0_0, tops_jtag0_1, wo0_jtag, wo1_jtag, wo2_jtag] 232 - if: 233 properties: 234 function: 235 const: int_usxgmii 236 then: 237 properties: 238 groups: 239 const: int_usxgmii 240 - if: 241 properties: 242 function: 243 const: dfd 244 then: 245 properties: 246 groups: 247 const: dfd 248 - if: 249 properties: 250 function: 251 const: flash 252 then: 253 properties: 254 groups: 255 enum: [emmc_45, emmc_51, sdcard, snfi] 256 - if: 257 properties: 258 function: 259 const: eth 260 then: 261 properties: 262 groups: 263 enum: [2p5g_ext_mdio, gbe_ext_mdio, mdc_mdio0, mdc_mdio1] 264 - if: 265 properties: 266 function: 267 const: i2c 268 then: 269 properties: 270 groups: 271 enum: [xfi_phy0_i2c0, xfi_phy1_i2c0, xfi_phy_pll_i2c0, 272 xfi_phy_pll_i2c1, i2c0_0, i2c1_sfp, xfi_pextp_phy0_i2c, 273 xfi_pextp_phy1_i2c, i2c0_1, u30_phy_i2c0, u32_phy_i2c0, 274 xfi_phy0_i2c1, xfi_phy1_i2c1, xfi_phy_pll_i2c2, i2c1_0, 275 u30_phy_i2c1, u32_phy_i2c1, xfi_phy_pll_i2c3, sgmii0_i2c, 276 sgmii1_i2c, i2c1_2, i2c2_0, i2c2_1] 277 - if: 278 properties: 279 function: 280 const: led 281 then: 282 properties: 283 groups: 284 enum: [2p5gbe_led0, 2p5gbe_led1, gbe0_led0, gbe0_led1, gbe1_led0, gbe1_led1, 285 gbe2_led0, gbe2_led1, gbe3_led0, gbe3_led1, wf5g_led0, wf5g_led1] 286 - if: 287 properties: 288 function: 289 const: pcie 290 then: 291 properties: 292 groups: 293 items: 294 enum: [pcie_wake_n0_0, pcie_clk_req_n0_0, pcie_wake_n3_0, 295 pcie_clk_req_n3, pcie_p0_phy_i2c, pcie_p1_phy_i2c, 296 pcie_p3_phy_i2c, pcie_p2_phy_i2c, ckm_phy_i2c, 297 pcie_wake_n0_1, pcie_wake_n3_1, pcie_2l_0_pereset, 298 pcie_1l_1_pereset, pcie_clk_req_n2_1, pcie_2l_1_pereset, 299 pcie_1l_0_pereset, pcie_wake_n1_0, pcie_clk_req_n1, 300 pcie_wake_n2_0, pcie_clk_req_n2_0, pcie_wake_n2_1, 301 pcie_clk_req_n0_1] 302 maxItems: 3 303 - if: 304 properties: 305 function: 306 const: pmic 307 then: 308 properties: 309 groups: 310 const: pmic 311 - if: 312 properties: 313 function: 314 const: pwm 315 then: 316 properties: 317 groups: 318 items: 319 enum: [pwm0, pwm1, pwm2, pwm2_0, pwm3, pwm3_0, pwm4, pwm4_0, pwm5, pwm5_0, 320 pwm6, pwm6_0, pwm7, pwm7_0] 321 maxItems: 2 322 - if: 323 properties: 324 function: 325 const: spi 326 then: 327 properties: 328 groups: 329 items: 330 enum: [spi0, spi0_wp_hold, spi1, spi2, spi2_wp_hold] 331 maxItems: 2 332 - if: 333 properties: 334 function: 335 const: uart 336 then: 337 properties: 338 groups: 339 items: 340 enum: [net_wo0_uart_txd_0, net_wo0_uart_txd_1, net_wo1_uart_txd_0, 341 net_wo1_uart_txd_1, net_wo2_uart_txd_0, net_wo2_uart_txd_1, 342 tops_uart0_0, tops_uart0_1, tops_uart0_2, tops_uart1_0, 343 tops_uart1_1, tops_uart1_2, uart0, uart1_0, uart1_1, uart1_2, 344 uart1_2_lite, uart2, uart2_0, uart2_1, uart2_3] 345 maxItems: 2 346 - if: 347 properties: 348 function: 349 const: watchdog 350 then: 351 properties: 352 groups: 353 const: watchdog 354 - if: 355 properties: 356 function: 357 const: udi 358 then: 359 properties: 360 groups: 361 const: udi 362 - if: 363 properties: 364 function: 365 const: usb 366 then: 367 properties: 368 groups: 369 items: 370 enum: [drv_vbus, drv_vbus_p1] 371 maxItems: 1 372 373 patternProperties: 374 '^conf(-[-a-z]*)?$': 375 type: object 376 additionalProperties: false 377 description: 378 pinconf configuration nodes. 379 $ref: /schemas/pinctrl/pincfg-node.yaml 380 381 properties: 382 pins: 383 description: 384 An array of strings. Each string contains the name of a pin. 385 items: 386 enum: [UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, GPIO_A, SMI_0_MDC, 387 SMI_0_MDIO, PCIE30_2L_0_WAKE_N, PCIE30_2L_0_CLKREQ_N, 388 PCIE30_1L_1_WAKE_N, PCIE30_1L_1_CLKREQ_N, GPIO_P, WATCHDOG, 389 GPIO_RESET, GPIO_WPS, PMIC_I2C_SCL, PMIC_I2C_SDA, I2C_1_SCL, 390 I2C_1_SDA, PCIE30_2L_0_PRESET_N, PCIE30_1L_1_PRESET_N, PWMD1, 391 SPI0_WP, SPI0_HOLD, SPI0_CSB, SPI0_MISO, SPI0_MOSI, SPI0_CLK, 392 SPI1_CSB, SPI1_MISO, SPI1_MOSI, SPI1_CLK, SPI2_CLK, SPI2_MOSI, 393 SPI2_MISO, SPI2_CSB, SPI2_HOLD, SPI2_WP, EMMC_RSTB, EMMC_DSL, 394 EMMC_CK, EMMC_CMD, EMMC_DATA_7, EMMC_DATA_6, EMMC_DATA_5, 395 EMMC_DATA_4, EMMC_DATA_3, EMMC_DATA_2, EMMC_DATA_1, 396 EMMC_DATA_0, PCM_FS_I2S_LRCK, PCM_CLK_I2S_BCLK, 397 PCM_DRX_I2S_DIN, PCM_DTX_I2S_DOUT, PCM_MCK_I2S_MCLK, 398 UART0_RXD, UART0_TXD, PWMD0, JTAG_JTDI, JTAG_JTDO, JTAG_JTMS, 399 JTAG_JTCLK, JTAG_JTRST_N, USB_DRV_VBUS_P1, LED_A, LED_B, LED_C, 400 LED_D, LED_E, GPIO_B, GPIO_C, I2C_2_SCL, I2C_2_SDA, 401 PCIE30_2L_1_PRESET_N, PCIE30_1L_0_PRESET_N, 402 PCIE30_2L_1_WAKE_N, PCIE30_2L_1_CLKREQ_N, 403 PCIE30_1L_0_WAKE_N, PCIE30_1L_0_CLKREQ_N, USB_DRV_VBUS_P0, 404 UART1_RXD, UART1_TXD, UART1_CTS, UART1_RTS] 405 maxItems: 84 406 407 bias-disable: true 408 409 bias-pull-up: 410 oneOf: 411 - type: boolean 412 description: normal pull up. 413 - enum: [100, 101, 102, 103] 414 description: 415 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in 416 dt-bindings/pinctrl/mt65xx.h. 417 418 bias-pull-down: 419 oneOf: 420 - type: boolean 421 description: normal pull down. 422 - enum: [100, 101, 102, 103] 423 description: 424 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in 425 dt-bindings/pinctrl/mt65xx.h. 426 427 input-enable: true 428 429 input-disable: true 430 431 output-enable: true 432 433 output-low: true 434 435 output-high: true 436 437 input-schmitt-enable: true 438 439 input-schmitt-disable: true 440 441 drive-strength: 442 enum: [2, 4, 6, 8, 10, 12, 14, 16] 443 444 mediatek,pull-up-adv: 445 description: | 446 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 447 Pull up settings for 2 pull resistors, R0 and R1. Valid arguments 448 are described as below: 449 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 450 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 451 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 452 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 453 $ref: /schemas/types.yaml#/definitions/uint32 454 enum: [0, 1, 2, 3] 455 456 mediatek,pull-down-adv: 457 description: | 458 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 459 Pull down settings for 2 pull resistors, R0 and R1. Valid arguments 460 are described as below: 461 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 462 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 463 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 464 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 465 $ref: /schemas/types.yaml#/definitions/uint32 466 enum: [0, 1, 2, 3] 467 468 required: 469 - pins 470 471additionalProperties: false 472 473examples: 474 - | 475 #include <dt-bindings/interrupt-controller/irq.h> 476 #include <dt-bindings/interrupt-controller/arm-gic.h> 477 #include <dt-bindings/pinctrl/mt65xx.h> 478 479 soc { 480 #address-cells = <2>; 481 #size-cells = <2>; 482 483 pio: pinctrl@1001f000 { 484 compatible = "mediatek,mt7988-pinctrl"; 485 reg = <0 0x1001f000 0 0x1000>, 486 <0 0x11c10000 0 0x1000>, 487 <0 0x11d00000 0 0x1000>, 488 <0 0x11d20000 0 0x1000>, 489 <0 0x11e00000 0 0x1000>, 490 <0 0x11f00000 0 0x1000>, 491 <0 0x1000b000 0 0x1000>; 492 reg-names = "gpio", "iocfg_tr", 493 "iocfg_br", "iocfg_rb", 494 "iocfg_lb", "iocfg_tl", "eint"; 495 gpio-controller; 496 #gpio-cells = <2>; 497 gpio-ranges = <&pio 0 0 84>; 498 interrupt-controller; 499 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 500 interrupt-parent = <&gic>; 501 #interrupt-cells = <2>; 502 503 i2c0_pins: i2c0-g0-pins { 504 mux { 505 function = "i2c"; 506 groups = "i2c0_1"; 507 }; 508 }; 509 510 mdio0_pins: mdio0-pins { 511 mux { 512 function = "eth"; 513 groups = "mdc_mdio0"; 514 }; 515 516 conf { 517 pins = "SMI_0_MDC", "SMI_0_MDIO"; 518 drive-strength = <8>; 519 }; 520 }; 521 522 mmc0_pins_emmc_51: mmc0-emmc-51-pins { 523 mux { 524 function = "flash"; 525 groups = "emmc_51"; 526 }; 527 }; 528 529 mmc0_pins_sdcard: mmc0-sdcard-pins { 530 mux { 531 function = "flash"; 532 groups = "sdcard"; 533 }; 534 }; 535 536 pcie0_pins: pcie0-pins { 537 mux { 538 function = "pcie"; 539 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", 540 "pcie_wake_n0_0"; 541 }; 542 }; 543 544 pcie1_pins: pcie1-pins { 545 mux { 546 function = "pcie"; 547 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", 548 "pcie_wake_n1_0"; 549 }; 550 }; 551 552 pcie2_pins: pcie2-pins { 553 mux { 554 function = "pcie"; 555 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", 556 "pcie_wake_n2_0"; 557 }; 558 }; 559 560 pcie3_pins: pcie3-pins { 561 mux { 562 function = "pcie"; 563 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", 564 "pcie_wake_n3_0"; 565 }; 566 }; 567 568 uart0_pins: uart0-pins { 569 mux { 570 function = "uart"; 571 groups = "uart0"; 572 }; 573 }; 574 }; 575 }; 576