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/linux/drivers/media/pci/ivtv/
H A Divtv-udma.c12 #include "ivtv-udma.h"
82 if (itv->udma.SG_handle == 0) { in ivtv_udma_alloc()
84 itv->udma.SG_handle = dma_map_single(&itv->pdev->dev, in ivtv_udma_alloc()
85 itv->udma.SGarray, in ivtv_udma_alloc()
86 sizeof(itv->udma.SGarray), in ivtv_udma_alloc()
96 struct ivtv_user_dma *dma = &itv->udma; in ivtv_udma_setup()
163 struct ivtv_user_dma *dma = &itv->udma; in ivtv_udma_unmap()
189 if (itv->udma.SG_handle) { in ivtv_udma_free()
190 dma_unmap_single(&itv->pdev->dev, itv->udma.SG_handle, in ivtv_udma_free()
191 sizeof(itv->udma.SGarray), DMA_TO_DEVICE); in ivtv_udma_free()
[all …]
H A Divtv-udma.h26 dma_sync_single_for_device(&itv->pdev->dev, itv->udma.SG_handle, in ivtv_udma_sync_for_device()
27 sizeof(itv->udma.SGarray), DMA_TO_DEVICE); in ivtv_udma_sync_for_device()
32 dma_sync_single_for_cpu(&itv->pdev->dev, itv->udma.SG_handle, in ivtv_udma_sync_for_cpu()
33 sizeof(itv->udma.SGarray), DMA_TO_DEVICE); in ivtv_udma_sync_for_cpu()
/linux/Documentation/devicetree/bindings/dma/ti/
H A Dk3-udma.yaml6 $id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
15 The UDMA-P is intended to perform similar (but significantly upgraded)
16 functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
18 The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
31 The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
32 channels. Channels in the UDMA-P can be configured to be either Packet-Based
37 The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
74 - description: UDMA-P Control /Status Registers region
99 Array of UDMA tchan resource subtypes for resource allocation for this
108 Array of UDMA rchan resource subtypes for resource allocation for this
[all …]
/linux/drivers/ata/
H A Dpata_amd.c77 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1; in timing_setup()
78 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15; in timing_setup()
99 t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03; in timing_setup()
103 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03; in timing_setup()
107 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03; in timing_setup()
111 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03; in timing_setup()
118 /* UDMA timing */ in timing_setup()
119 if (at.udma) in timing_setup()
237 * Program the MWDMA/UDMA modes for the AMD and Nvidia
275 u32 saved_udma, udma; in nv_mode_filter() local
[all …]
H A Dpata_via.c13 * VIA VT82C586a - Added UDMA to 33Mhz
195 /* UDMA 66 chips have only drive side logic */ in via_cable_detect()
198 /* UDMA 100 or later */ in via_cable_detect()
236 * @udma_type: UDMA mode/format of registers
294 /* Load the UDMA bits according to type */ in via_do_set_mode()
298 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03; in via_do_set_mode()
301 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f; in via_do_set_mode()
304 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; in via_do_set_mode()
307 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; in via_do_set_mode()
311 /* Set UDMA unless device is not UDMA capable */ in via_do_set_mode()
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H A Dpata_it821x.c60 * non UDMA devices restrict each others performance. It also has a
95 u16 udma[2]; /* Cached UDMA values (per drive) */ member
143 * it821x_program_udma - program the UDMA registers
148 * Program the UDMA timing for this drive according to the
150 * the errata on the 0x10 revision. The UDMA errata is partly handled
162 /* Program UDMA timing bits */ in it821x_program_udma()
229 * Reprogram the UDMA/PIO of the pair drive for the switch in it821x_clock_strategy()
232 if (pair && itdev->udma[1-unit] != UDMA_OFF) { in it821x_clock_strategy()
233 it821x_program_udma(ap, pair, itdev->udma[1-unit]); in it821x_clock_strategy()
237 * Reprogram the UDMA/PIO of our drive for the switch. in it821x_clock_strategy()
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H A Dpata_serverworks.c20 * supports UDMA mode 2 (33 MB/s)
23 * all revisions support UDMA mode 4 (66 MB/s)
24 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
50 * Seagate Barracuda ATA IV Family drives in UDMA mode 5
150 * specific rules. OSB4 requires no UDMA for disks due to a FIFO
177 /* Disk, UDMA */ in serverworks_csb_filter()
224 * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
226 * while the chipset uses mode number for UDMA.
291 dev_info(&pdev->dev, "UDMA not BIOS enabled.\n"); in serverworks_fixup_osb4()
292 reg |= 0x00004000; /* enable UDMA/33 support */ in serverworks_fixup_osb4()
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H A Dpata_artop.c93 * matching PIO clocking for UDMA, as well as the MWDMA timings.
118 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
119 * the event UDMA is used the later call to set_dmamode will set the
134 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ in artop6210_set_piomode()
172 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
173 * the event UDMA is used the later call to set_dmamode will set the
187 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ in artop6260_set_piomode()
222 /* Add ultra DMA bits if in UDMA mode */ in artop6210_set_dmamode()
258 /* Add ultra DMA bits if in UDMA mode */ in artop6260_set_dmamode()
322 /* BIOS may have left us in UDMA, clear it before libata probe */ in atp8xx_fixup()
H A Dpata_ali.c115 * fix that later on. Also ensure we do not do UDMA on WDC drives
163 * @ultra: UDMA timing or zero for off
165 * Loads the timing registers for cmd/data and disable UDMA if
166 * ultra is zero. If ultra is set then load and enable the UDMA
176 int udmat = 0x56 + ap->port_no; /* UDMA timing */ in ali_program_modes()
178 u8 udma; in ali_program_modes() local
192 /* Set up the UDMA enable */ in ali_program_modes()
193 pci_read_config_byte(pdev, udmat, &udma); in ali_program_modes()
194 udma &= ~(0x0F << shift); in ali_program_modes()
195 udma |= ultra << shift; in ali_program_modes()
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H A Dpata_rdc.c149 /* Ensure the UDMA bit is off - it will be turned back on if in rdc_set_piomode()
150 UDMA is selected */ in rdc_set_piomode()
164 * Set UDMA mode for device, in host controller PCI config space.
193 unsigned int udma = adev->dma_mode - XFER_UDMA_0; in rdc_set_dmamode() local
199 * UDMA is handled by a combination of clock switching and in rdc_set_dmamode()
205 u_speed = min(2 - (udma & 1), udma); in rdc_set_dmamode()
206 if (udma == 5) in rdc_set_dmamode()
208 else if (udma > 2) in rdc_set_dmamode()
H A Dpata_pdc2027x.c93 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
94 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
95 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
96 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
97 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
98 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
99 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
251 * Block UDMA on devices that cause trouble with this controller.
265 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */ in pdc2027x_mode_filter()
315 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
[all …]
H A Dlibata-pata-timings.c18 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
71 q->udma = EZ(t->udma, UT); in ata_timing_quantize()
94 m->udma = max(a->udma, b->udma); in ata_timing_merge()
158 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, in ata_timing_compute()
H A Dpata_atiixp.c52 u8 udma; in atiixp_cable_detect() local
59 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); in atiixp_cable_detect()
60 if ((udma & 0x07) >= 0x04 || (udma & 0x70) >= 0x40) in atiixp_cable_detect()
205 * When DMA begins we need to ensure that the UDMA control
234 * DMA has completed. Clear the UDMA flag as the next operations will
235 * be PIO ones not UDMA data transfer.
H A Dpata_it8213.c133 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
159 unsigned int udma = adev->dma_mode - XFER_UDMA_0; in it8213_set_dmamode() local
165 u_speed = min(2 - (udma & 1), udma); in it8213_set_dmamode()
166 if (udma > 4) in it8213_set_dmamode()
168 else if (udma > 2) in it8213_set_dmamode()
175 /* Load the UDMA cycle time */ in it8213_set_dmamode()
H A Dpata_sis.c328 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
329 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
354 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ in sis_old_set_dmamode()
367 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
382 /* MWDMA 0-2 and UDMA 0-5 */ in sis_66_set_dmamode()
390 the higher bits are dependent on the device, bit 15 udma */ in sis_66_set_dmamode()
394 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ in sis_66_set_dmamode()
407 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
428 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ in sis_100_set_dmamode()
441 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
[all …]
H A Dpata_hpt3x3.c33 * all we have to do is clear the MWDMA and UDMA bits then load the
48 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */ in hpt3x3_set_piomode()
60 * Set up the channel for MWDMA or UDMA modes. Much the same as with
61 * PIO, load the mode number and then set MWDMA or UDMA flag.
64 * 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
79 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */ in hpt3x3_set_dmamode()
H A Dpata_optidma.c16 * but we do handle UDMA.
22 * UDMA requires a 66MHz FSB
195 * The Firestar plus has additional UDMA functionality for UDMA0-2 and
208 int udma = mode - XFER_UDMA_0; in optiplus_mode_setup() local
219 udslave |= (udma << dev2); in optiplus_mode_setup()
223 udcfg |= (udma << dev2); in optiplus_mode_setup()
357 * optiplus_with_udma - Look for UDMA capable setup
393 printk(KERN_WARNING "UDMA not supported in this configuration.\n"); in optiplus_with_udma()
H A Dpata_cs5530.c68 * We cannot mix MWDMA and UDMA without reloading timings each switch
104 tuning |= 0x00100000; /* UDMA for both */ in cs5530_set_dmamode()
128 * one MWDMA/UDMA bit.
139 /* Maybe, but do the channels match MWDMA/UDMA ? */ in cs5530_qc_issue()
230 * Disable trapping of UDMA register accesses (Win98 hack): in cs5530_init_chip()
292 /* The docking connector doesn't do UDMA, and it seems not MWDMA */ in cs5530_init_one()
H A Data_piix.c45 * PIIX4 errata #10 - BM IDE hang with non UDMA
57 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
124 ich_pata_33, /* ICH up to UDMA 33 only */
126 ich_pata_100, /* ICH up to UDMA 100 */
127 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
160 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
169 /* Intel ICH (i810, i815, i840) UDMA 66*/
171 /* Intel ICH0 : UDMA 33*/
175 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
179 /* Intel ICH3 (E7500/1) UDMA 100 */
[all …]
H A Dpata_mpc52xx.c9 * UDMA support based on patches by Freescale (Bernard Kuhn, John Rigby),
104 /* ATAPI-4 UDMA specs (in clocks) */
188 #define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */
197 #define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */
201 #define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */
216 u32 udma1; /* ATA + 0x18 UDMA Timing 1 */
217 u32 udma2; /* ATA + 0x1c UDMA Timing 2 */
218 u32 udma3; /* ATA + 0x20 UDMA Timing 3 */
219 u32 udma4; /* ATA + 0x24 UDMA Timing 4 */
220 u32 udma5; /* ATA + 0x28 UDMA Timing 5 */
[all …]
H A Dpata_cmd64x.c218 regU |= 1 << adev->devno; /* UDMA on */ in cmd64x_set_dmamode()
222 regU &= ~ (1 << adev->devno); /* UDMA off */ in cmd64x_set_dmamode()
380 { /* CMD 643 - no UDMA */ in cmd64x_init_one()
386 { /* CMD 646 with broken UDMA */ in cmd64x_init_one()
392 { /* CMD 646U with broken UDMA */ in cmd64x_init_one()
398 { /* CMD 646U2 with working UDMA */ in cmd64x_init_one()
449 /* UDMA works since rev 5 */ in cmd64x_init_one()
H A Dpata_efar.c11 * Intel ICH controllers the EFAR widened the UDMA mode register bits
152 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
181 unsigned int udma = adev->dma_mode - XFER_UDMA_0; in efar_set_dmamode() local
186 /* Load the UDMA mode number */ in efar_set_dmamode()
189 udma_timing |= udma << (4 * devid); in efar_set_dmamode()
/linux/Documentation/devicetree/bindings/ata/
H A Dpata-arasan.txt21 - arasan,broken-udma: if present, UDMA mode is unusable
25 required unless both UDMA and MWDMA mode are broken
/linux/drivers/dma/ti/
H A DKconfig38 tristate "Texas Instruments UDMA support"
47 Enable support for the TI UDMA (Unified DMA) controller. This
51 tristate "Texas Instruments UDMA Glue layer for non DMAengine users"
/linux/sound/soc/ti/
H A DMakefile6 snd-soc-ti-udma-y := udma-pcm.o
10 obj-$(CONFIG_SND_SOC_TI_UDMA_PCM) += snd-soc-ti-udma.o

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