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/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Driscv,pmu.yaml123 * This example also binds standard SBI PMU hardware IDs to U74 PMU event
124 * codes, U74 uses a bitfield for events encoding, so several U74 events
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zcu106-revA.dts133 ina226-u74 {
135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
423 u74: ina226@46 { /* u74 */ label
426 label = "ina226-u74";
H A Dzynqmp-zcu102-revA.dts133 ina226-u74 {
135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
412 u74: ina226@46 { /* u74 */ label
415 label = "ina226-u74";
H A Dzynqmp-zcu111-revA.dts368 /* u74 IR38060 +2 */
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml47 - sifive,u74
48 - sifive,u74-mc
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100.dtsi21 compatible = "sifive,u74-mc", "riscv";
50 compatible = "sifive,u74-mc", "riscv";
H A Djh7110.dtsi44 compatible = "sifive,u74-mc", "riscv";
77 compatible = "sifive,u74-mc", "riscv";
110 compatible = "sifive,u74-mc", "riscv";
143 compatible = "sifive,u74-mc", "riscv";
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVProcessors.td205 def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DHost.cpp454 .Case("sifive,u74-mc", "sifive-u74") in getHostCPUNameForRISCV()
455 .Case("sifive,bullet0", "sifive-u74") in getHostCPUNameForRISCV()