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1 SiFive Platform-Level Interrupt Controller (PLIC)2 -------------------------------------------------4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller5 (PLIC) high-level specification in the RISC-V Privileged Architecture10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two13 Each interrupt can be enabled on per-context basis. Any context can claim21 While the PLIC supports both edge-triggered and level-triggered interrupts,23 specified in the PLIC device-tree binding.25 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that[all …]
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause4 ---5 $id: http://devicetree.org/schemas/interrupt-controlle[all...]