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/linux/drivers/gpu/drm/xe/
H A D	xe_gt_sriov_pf_control_types.h	16 * @XE_GT_SRIOV_STATE_WIP: indicates that some operations are in progress. 17 * @XE_GT_SRIOV_STATE_FLR_WIP: indicates that a VF FLR is in progress. 18 * @XE_GT_SRIOV_STATE_FLR_SEND_START: indicates that the PF wants to send a FLR START command. 19 * @XE_GT_SRIOV_STATE_FLR_WAIT_GUC: indicates that the PF awaits for a response from the GuC. 20 * @XE_GT_SRIOV_STATE_FLR_GUC_DONE: indicates that the PF has received a response from the GuC. 21 * @XE_GT_SRIOV_STATE_FLR_RESET_CONFIG: indicates that the PF needs to clear VF's resources. 22 * @XE_GT_SRIOV_STATE_FLR_RESET_DATA: indicates that the PF needs to clear VF's data. 23 * @XE_GT_SRIOV_STATE_FLR_RESET_MMIO: indicates that the PF needs to reset VF's registers. 24 * @XE_GT_SRIOV_STATE_FLR_SEND_FINISH: indicates that the PF wants to send a FLR FINISH message. 25 * @XE_GT_SRIOV_STATE_FLR_FAILED: indicates that VF FLR sequence failed. [all …]
/linux/Documentation/process/
H A D	management-style.rst	14 to do with reality. It started as a lark, but that doesn't mean that it 27 making it painfully obvious to the questioner that we don't have a clue 37 Everybody thinks managers make decisions, and that decision-making is 39 manager must be to make it. That's very deep and obvious, but it's not 47 competent to make that decision for them. 51 Namely that you are in the wrong job, and that they should be managing 60 It helps to realize that the key difference between a big decision and a 62 can be made small by just always making sure that if you were wrong (and 67 And people will even see that as true leadership (cough bullshit 71 things that can't be undone. Don't get ushered into a corner from which [all …]
H A D	6.Followthrough.rst	8 patches. One of the biggest mistakes that even experienced kernel 9 developers can make is to conclude that their work is now done. In truth, 13 It is a rare patch which is so good at its first posting that there is no 16 code. You, as the author of that code, will be expected to work with the 17 kernel community to ensure that your code is up to the kernel's quality 32 value and why you went to the trouble of writing it. But that value 36 to substantial rewrites - come from the understanding that Linux will 49 be working on the kernel years from now, but they understand that their 57 the same. Sometimes this means that the clever hack in your driver 61 What all of this comes down to is that, when reviewers send you comments, [all …]
H A D	handling-regressions.rst	10 user's point of view; if you never read that text, go and at least skim over it 20 * When receiving a mailed report that did not CC the list, bring it into the 47 only fixing part of the issue that caused the regression, you may use 71 * When you receive a report by mail that did not CC the list, immediately bring 73 try to ensure it gets CCed again in case you reply to a reply that omitted 96 you want to see tracked; that's important, as regzbot will later look out 107 Regzbot will then automatically associate patches with the report that 133 these tags are of great value for everyone (you included) that might be looking 146 * Run a kernel with a regression that impacts usage. 156 How to realize that in practice depends on various factors. Use the following [all …]
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A D	other.json	9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol… 12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old… 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmont/
H A D	cache.json	7 …on which likely indicates back pressure from L2Q. It also counts requests that would have gone dir… 24 …"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That … 33 …"PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects… 41 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", 50 …"PublicDescription": "Counts memory requests originating from the core that reference a cache line… 55 "BriefDescription": "Loads retired that came from DRAM (Precise event capable)", 72 …that when the load address was checked by other caching agents (typically another processor) in th… 77 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 83 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 88 "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)", [all …]
/linux/tools/memory-model/Documentation/
H A D	glossary.txt	9 dependency" extends from that load extending to the later access. 20 address dependency extends from that rcu_dereference() to that 27 Acquire: With respect to a lock, acquiring that lock, for example, 29 a special operation that includes a load and which orders that 30 load before later memory references running on that same CPU. 36 to that same variable, (in other words, the acquire load "reads 37 from" the release store), then all operations preceding that 38 store "happen before" any operations following that loa [all...]
/linux/LICENSES/preferred/
H A D	LGPL-2.1	45 price. Our General Public Licenses are designed to make sure that you have 47 service if you wish); that you receive source code or can get it if you 48 want it; that you can change the software and use pieces of it in new free 49 programs; and that you are informed that you can do these things. 51 To protect your rights, we need to make restrictions that forbid 57 a fee, you must give the recipients all the rights that we gave you. You 58 must make sure that they, too, receive or can get the source code. If you 60 the recipients, so that they can relink them with the library after making 68 To protect each distributor, we want to make it very clear that there is no 70 else and passed on, the recipients should know that what they have is not [all …]
H A D	LGPL-2.0	39 General Public Licenses are designed to make sure that you have the freedom 41 wish), that you receive source code or can get it if you want it, that you 42 can change the software or use pieces of it in new free programs; and that 45 To protect your rights, we need to make restrictions that forbid anyone to 51 a fee, you must give the recipients all the rights that we gave you. You 52 must make sure that they, too, receive or can get the source code. If you 54 the recipients so that they can relink them with the library, after making 62 Also, for each distributor's protection, we want to make certain that 63 everyone understands that there is no warranty for this free library. If 65 recipients to know that what they have is not the original version, so that [all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	memory.json	11 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for r… 21 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for d… 31 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for d… 41 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for r… 51 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for d… 61 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for d… 71 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 81 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 91 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 101 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… [all …]
H A D	cache.json	3 …"BriefDescription": "Counts the number of MEC requests that were not accepted into the L2Q because… 42 …that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache … 67 …"BriefDescription": "Counts the loads retired that get the data from the other core in the same ti… 73 …"PublicDescription": "This event counts the number of load micro-ops retired that got data from an… 78 "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache", 82 …: "This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that pr… 87 …"BriefDescription": "Counts the number of load micro-ops retired that hit in the L2 (Precise Event… 93 …"PublicDescription": "This event counts the number of load micro-uops retired that hit in the L2 (… 98 …"BriefDescription": "Counts the number of load micro-ops retired that miss in the L2 (Precise Even… 104 …"PublicDescription": "This event counts the number of load micro-ops retired that miss in the L2 (… [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	core-imp-def.json	15 "PublicDescription": "Predictable branch speculatively executed that hit any level of BTB", 18 "BriefDescription": "Predictable branch speculatively executed that hit any level of BTB" 21 …"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of … 24 …"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of B… 27 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 30 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 33 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 36 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 39 …"PublicDescription": "Predictable unconditional branch speculatively executed that did not hit any… 42 …"BriefDescription": "Predictable unconditional branch speculatively executed that did not hit any … [all …]
/linux/Documentation/admin-guide/
H A D	reporting-issues.rst	15 you don't find any, install `the latest release from that series 31 If it shows the problem, search for the change that fixed it in mainline and 47 Once the report is out, answer any questions that come up and help where you 48 can. That includes keeping the ball rolling by occasionally retesting with newer 55 developers. It might be all that's needed for people already familiar with 63 a slightly different order. That's in your interest, to make sure you notice 64 early if an issue that looks like a Linux kernel problem is actually caused by 80 issue, or a really severe problem: those are 'issues of high priority' that 81 need special handling in some steps that are about to follow. 83 * Make sure it's not the kernel's surroundings that are causing the issue [all …]
/linux/include/kunit/
H A D	test.h	98 * that makes expectations and assertions (see KUNIT_EXPECT_TRUE() and 196 * is used to lazily generate a series of arbitrarily typed values that fit into 232 * A kunit_suite is a collection of related &struct kunit_case s, such that 237 * Note that @exit and @suite_exit will run even if @init or @suite_init 298 * Because resources is a list that may be updated multiple times (with 395 * This functions similar to kunit_test_suites() except that it compiles the 399 * _probe; so that modpost suppresses warnings about referencing init data 431 * Note that some internal context data is also allocated with GFP_KERNEL, 444 * Note that some internal context data is also allocated with GFP_KERNEL, 653 * The opposite of KUNIT_FAIL(), it is an expectation that cannot fail. In other [all …]
/linux/Documentation/filesystems/
H A D	directory-locking.rst	12 that "inode pointer" order in the following. 37 * check that the source is not a directory 40 5. rename that is _not_ cross-directory. Locking rules: 47 * take the locks that need to be taken (exclusive), in inode pointer order 48 if need to take both (that can happen only when both source and target 51 allowed only with RENAME_EXCHANGE, and that won't be removing the target). 60 * verify that the source is not a descendent of the target and 65 The rules above obviously guarantee that all directories that are going 78 that's not a problem, but there is a nasty twist - what should we do 79 when one growing tree reaches the root of another? That can happen in [all …]
/linux/Documentation/maintainer/
H A D	rebasing-and-merging.rst	12 those tools incorrectly, but avoiding problems is not actually all that 15 One thing to be aware of in general is that, unlike many other projects, 26 within a repository. There are two different types of operations that are 43 history; used improperly, it can obscure that history and introduce bugs. 45 There are a few rules of thumb that can help developers to avoid the worst 48 - History that has been exposed to the world beyond your private system 51 work is in need of rebasing, that is usually a sign that it is not yet 54 That said, there are always exceptions. Some trees (linux-next being 58 testing services. If you do expose a branch that may be unstable in 59 this way, be sure that prospective users know not to base work on it. [all …]
/linux/tools/perf/pmu-events/arch/x86/silvermont/
H A D	cache.json	3 …"BriefDescription": "Counts the number of request that were not accepted into the L2Q because the … 7 …that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, … 15 …that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to acc… 20 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ", 24 …"PublicDescription": "This event counts the number of demand and prefetch transactions that the L2… 41 …"PublicDescription": "This event counts requests originating from the core that references a cache… 69 …"PublicDescription": "This event counts the number of load ops retired that got data from the othe… 78 …ption": "This event counts the number of load ops retired that miss in L1 Data cache. Note that pr… 88 "PublicDescription": "This event counts the number of load ops retired that hit in the L2.", 98 … "PublicDescription": "This event counts the number of load ops retired that miss in the L2.", [all …]
/linux/Documentation/RCU/
H A D	checklist.rst	9 that make use of RCU. Violating any of the rules listed below will 10 result in the same sorts of problems that leaving out a locking primitive 17 performance measurements show that RCU is nonetheless the right 36 of lockless algorithms that garbage collectors do. 54 relating to itself that other tasks can read, there by definition 55 can be no bottleneck). Note that the definition of "large" has 74 Please note that you cannot rely on code known to be built 87 any locks or atomic operations. This means that readers will 94 RCU-protected data structures that have been added to 100 locks (that are acquired by both readers and writers) [all …]
/linux/Documentation/locking/
H A D	rt-mutex-design.rst	11 It doesn't describe the reasons why rtmutex.c exists. For that please see 13 that happen without this code, but that is in the concept to understand 17 inheritance (PI) algorithm that is used, as well as reasons for the 18 decisions that were made to implement PI in the manner that was done. 27 to use a resource that a lower priority process has (a mutex for example), 30 is something called unbounded priority inversion. That is when the high 37 that C owns and must wait and lets C run to release the lock. But in the 71 inherited priority, and A then can continue with the resource that C had. 76 Here I explain some terminology that is used in this document to help describe 77 the design that is used to implement PI. [all …]
/linux/Documentation/power/
H A D	freezing-of-tasks.rst	18 (TASK_FROZEN, TASK_FREEZABLE and __TASK_FREEZABLE_UNSAFE) used for that. 19 The tasks that have PF_NOFREEZE unset (all user space tasks and some kernel 30 try_to_freeze_tasks() that sends a fake signal to all user space processes, and 31 wakes up all the kernel threads. All freezable tasks must react to that by 34 it loop until it is woken by an explicit TASK_FROZEN wakeup. Then, that task 41 try_to_freeze() function (defined in include/linux/freezer.h), that checks 48 that put the task to sleep (TASK_INTERRUPTIBLE) or freeze it (TASK_FROZEN) if 79 order to wake up each frozen task. Then, the tasks that have been frozen leave 112 IV. Why do we do that? 122 filesystem-related information that must be consistent with the state of the [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	virtual-memory.json	3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 7 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 21 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 30 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 34 …"PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB le… 39 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 43 …"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB le… 48 … Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any pa… 57 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 65 … Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", [all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	virtual-memory.json	3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 7 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 21 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 30 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 34 …"PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB le… 39 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 43 …"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB le… 48 … Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any pa… 57 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 65 … Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", [all …]
/linux/Documentation/userspace-api/media/v4l/
H A D	colorspaces.rst	10 biology. Just because you have three numbers that describe the 'red', 11 'green' and 'blue' components of the color of a pixel does not mean that 12 you can accurately display that color. A colorspace defines what it 13 actually means to have an RGB value of e.g. (255, 0, 0). That is, 17 In order to do that we first need to have a good definition of color, 18 i.e. some way to uniquely and unambiguously define a color so that 20 the human eye has color receptors that are sensitive to three different 34 possible that different SPDs will result in the same stimulation of 39 between SPDs and the perceived color and that resulted in the CIE 1931 40 standard that defines spectral weighting functions that model the [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A D	core-imp-def.json	15 "PublicDescription": "Predictable branch speculatively executed that hit any level of BTB", 18 "BriefDescription": "Predictable branch speculatively executed that hit any level of BTB" 21 …"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of … 24 …"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of B… 27 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 30 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 33 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 36 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 39 …"PublicDescription": "Predictable unconditional branch speculatively executed that did not hit any… 42 …"BriefDescription": "Predictable unconditional branch speculatively executed that did not hit any … [all …]
/linux/Documentation/driver-api/pm/
H A D	cpuidle.rst	16 Every time one of the logical CPUs in the system (the entities that appear to 18 cores) is idle after an interrupt or equivalent wakeup event, which means that 20 with it, there is an opportunity to save energy for the processor that it 21 belongs to. That can be done by making the idle logical CPU stop fetching 25 However, there may be multiple different idle states that can be used in such a 27 (from the kernel perspective) and ask the processor to use (or "enter") that 28 particular idle state. That is the role of the CPU idle time management 32 principle, so the generic code that in principle need not depend on the hardware 33 or platform design details in it is separate from the code that interacts with 36 to enter, drivers that pass the governors' decisions on to the hardware and [all …]

12 3 4 5 6 7 8 9 10 >>...361