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/linux/drivers/char/hw_random/
H A Djh7110-trng.c3 * TRNG driver for the StarFive JH7110 SoC
24 /* trng register offset */
123 static inline int starfive_trng_wait_idle(struct starfive_trng *trng) in starfive_trng_wait_idle() argument
127 return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat, in starfive_trng_wait_idle()
133 static inline void starfive_trng_irq_mask_clear(struct starfive_trng *trng) in starfive_trng_irq_mask_clear() argument
136 u32 data = readl(trng->base + STARFIVE_ISTAT); in starfive_trng_irq_mask_clear()
138 writel(data, trng->base + STARFIVE_ISTAT); in starfive_trng_irq_mask_clear()
141 static int starfive_trng_cmd(struct starfive_trng *trng, u32 cmd, bool wait) in starfive_trng_cmd() argument
151 reinit_completion(&trng->random_done); in starfive_trng_cmd()
152 spin_lock_irq(&trng->write_lock); in starfive_trng_cmd()
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H A Datmel-rng.c43 static bool atmel_trng_wait_ready(struct atmel_trng *trng, bool wait) in atmel_trng_wait_ready() argument
47 ready = readl(trng->base + TRNG_ISR) & TRNG_ISR_DATRDY; in atmel_trng_wait_ready()
49 readl_poll_timeout(trng->base + TRNG_ISR, ready, in atmel_trng_wait_ready()
58 struct atmel_trng *trng = container_of(rng, struct atmel_trng, rng); in atmel_trng_read() local
62 ret = pm_runtime_get_sync((struct device *)trng->rng.priv); in atmel_trng_read()
64 pm_runtime_put_sync((struct device *)trng->rng.priv); in atmel_trng_read()
68 ret = atmel_trng_wait_ready(trng, wait); in atmel_trng_read()
72 *data = readl(trng->base + TRNG_ODATA); in atmel_trng_read()
78 readl(trng->base + TRNG_ISR); in atmel_trng_read()
82 pm_runtime_mark_last_busy((struct device *)trng->rng.priv); in atmel_trng_read()
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H A Dxiphera-trng.c24 /* trng statuses */
37 struct xiphera_trng *trng = container_of(rng, struct xiphera_trng, rng); in xiphera_trng_read() local
42 if (readl(trng->mem + STATUS_REG) == TRNG_NEW_RAND_AVAILABLE) { in xiphera_trng_read()
43 *(u32 *)buf = readl(trng->mem + RAND_REG); in xiphera_trng_read()
45 * Inform the trng of the read in xiphera_trng_read()
48 writel(HOST_TO_TRNG_READ, trng->mem + CONTROL_REG); in xiphera_trng_read()
49 writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG); in xiphera_trng_read()
63 struct xiphera_trng *trng; in xiphera_trng_probe() local
66 trng = devm_kzalloc(dev, sizeof(*trng), GFP_KERNEL); in xiphera_trng_probe()
67 if (!trng) in xiphera_trng_probe()
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H A Dexynos-trng.c85 struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv; in exynos_trng_do_read_reg() local
89 writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL); in exynos_trng_do_read_reg()
90 val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val, in exynos_trng_do_read_reg()
95 memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max); in exynos_trng_do_read_reg()
135 struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv; in exynos_trng_init_reg() local
139 sss_rate = clk_get_rate(trng->clk); in exynos_trng_init_reg()
142 * For most TRNG circuits the clock frequency of under 500 kHz in exynos_trng_init_reg()
147 dev_err(trng->dev, "clock divider too large: %d\n", val); in exynos_trng_init_reg()
151 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV); in exynos_trng_init_reg()
155 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL); in exynos_trng_init_reg()
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H A Dingenic-trng.c37 struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng); in ingenic_trng_init() local
40 ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET); in ingenic_trng_init()
42 writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET); in ingenic_trng_init()
49 struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng); in ingenic_trng_cleanup() local
52 ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET); in ingenic_trng_cleanup()
54 writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET); in ingenic_trng_cleanup()
59 struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng); in ingenic_trng_read() local
64 ret = readl_poll_timeout(trng->base + TRNG_REG_STATUS_OFFSET, status, in ingenic_trng_read()
71 *data = readl(trng->base + TRNG_REG_RANDOMNUM_OFFSET); in ingenic_trng_read()
78 struct ingenic_trng *trng; in ingenic_trng_probe() local
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H A Darm_smccc_trng.c3 * Randomness driver for the ARM SMCCC TRNG Firmware Interface
8 * The ARM TRNG firmware interface specifies a protocol to read entropy
99 struct hwrng *trng; in smccc_trng_probe() local
101 trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL); in smccc_trng_probe()
102 if (!trng) in smccc_trng_probe()
105 trng->name = "smccc_trng"; in smccc_trng_probe()
106 trng->read = smccc_trng_read; in smccc_trng_probe()
108 return devm_hwrng_register(&pdev->dev, trng); in smccc_trng_probe()
121 MODULE_DESCRIPTION("Arm SMCCC TRNG firmware interface support");
H A Ds390-trng.c3 * s390 TRNG device driver
5 * Driver for the TRNG (true random number generation) command
12 #define KMSG_COMPONENT "trng"
30 MODULE_DESCRIPTION("s390 CPACF TRNG device driver");
33 /* trng related debug feature things */
43 /* trng helpers */
115 "trng: %llu\n" in trng_counter_show()
147 .name = "trng",
187 * The trng is supposed to have 100% entropy, and thus we register with a very
192 .name = "s390-trng",
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H A DMakefile17 obj-$(CONFIG_HW_RANDOM_EXYNOS) += exynos-trng.o
26 obj-$(CONFIG_HW_RANDOM_INGENIC_TRNG) += ingenic-trng.o
42 obj-$(CONFIG_HW_RANDOM_S390) += s390-trng.o
47 obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
52 obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
H A Dpic32-rng.c34 * The TRNG can generate up to 24Mbps. This is a timeout that should be safe
35 * enough given the instructions in the loop and that the TRNG may not always
44 /* enable TRNG in enhanced mode */ in pic32_rng_init()
60 /* TRNG value comes through the seed registers */ in pic32_rng_read()
H A DKconfig282 module will be called ingenic-trng.
360 tristate "APM X-Gene True Random Number Generator (TRNG) support"
464 module will be called s390-trng.
478 will be called exynos-trng.
539 module will be called xiphera-trng.
542 tristate "Arm SMCCC TRNG firmware interface support"
547 the Arm SMCCC TRNG firmware interface. This reads entropy from
574 The module will be called jh7110-trng.
H A Dks-sa-rng.c28 /* TRNG enable control in SA System module*/
31 /* TRNG start control in TRNG module */
137 /* Disable all interrupts from TRNG */ in ks_sa_rng_init()
/linux/drivers/crypto/hisilicon/trng/
H A Dtrng.c61 struct hisi_trng *trng; member
67 static void hisi_trng_set_seed(struct hisi_trng *trng, const u8 *seed) in hisi_trng_set_seed() argument
79 writel(val, trng->base + SW_DRBG_SEED(seed_reg)); in hisi_trng_set_seed()
87 struct hisi_trng *trng = ctx->trng; in hisi_trng_seed() local
92 pr_err("slen(%u) is not matched with trng(%d)\n", slen, in hisi_trng_seed()
97 writel(0x0, trng->base + SW_DRBG_BLOCKS); in hisi_trng_seed()
98 hisi_trng_set_seed(trng, seed); in hisi_trng_seed()
101 trng->base + SW_DRBG_BLOCKS); in hisi_trng_seed()
102 writel(0x1, trng->base + SW_DRBG_INIT); in hisi_trng_seed()
104 ret = readl_relaxed_poll_timeout(trng->base + SW_DRBG_STATUS, in hisi_trng_seed()
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H A DMakefile1 obj-$(CONFIG_CRYPTO_DEV_HISI_TRNG) += hisi-trng-v2.o
2 hisi-trng-v2-objs = trng.o
/linux/drivers/crypto/allwinner/sun8i-ce/
H A Dsun8i-ce-trng.c3 * sun8i-ce-trng.c - hardware cryptographic offloader for
8 * This file handle the TRNG
17 * Note that according to the algorithm ID, 2 versions of the TRNG exists,
35 ce = container_of(rng, struct sun8i_ce_dev, trng); in sun8i_ce_trng_read()
68 common = ce->variant->trng | CE_COMM_INT; in sun8i_ce_trng_read()
84 err = sun8i_ce_run_task(ce, 3, "TRNG"); in sun8i_ce_trng_read()
105 if (ce->variant->trng == CE_ID_NOTSUPP) { in sun8i_ce_hwrng_register()
106 dev_info(ce->dev, "TRNG not supported\n"); in sun8i_ce_hwrng_register()
109 ce->trng.name = "sun8i Crypto Engine TRNG"; in sun8i_ce_hwrng_register()
110 ce->trng.read = sun8i_ce_trng_read; in sun8i_ce_hwrng_register()
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H A Dsun8i-ce.h137 * @trng_t_dlen_in_bytes: Does the request size for TRNG is in
142 * @trng: The CE_ALG_XXX value for the TRNG
156 unsigned char trng; member
237 struct hwrng trng; member
/linux/drivers/crypto/amcc/
H A Dcrypto4xx_trng.c74 struct device_node *trng = NULL; in ppc4xx_trng_probe() local
78 /* Find the TRNG device node and map it */ in ppc4xx_trng_probe()
79 trng = of_find_matching_node(NULL, ppc4xx_trng_match); in ppc4xx_trng_probe()
80 if (!trng || !of_device_is_available(trng)) { in ppc4xx_trng_probe()
81 of_node_put(trng); in ppc4xx_trng_probe()
85 dev->trng_base = of_iomap(trng, 0); in ppc4xx_trng_probe()
86 of_node_put(trng); in ppc4xx_trng_probe()
98 core_dev->trng = rng; in ppc4xx_trng_probe()
101 err = devm_hwrng_register(core_dev->device, core_dev->trng); in ppc4xx_trng_probe()
114 core_dev->trng = NULL; in ppc4xx_trng_probe()
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/linux/Documentation/devicetree/bindings/rng/
H A Datmel,at91-trng.yaml4 $id: http://devicetree.org/schemas/rng/atmel,at91-trng.yaml#
18 - atmel,at91sam9g45-trng
19 - microchip,sam9x60-trng
22 - microchip,sama7g5-trng
23 - const: atmel,at91sam9g45-trng
26 - microchip,sam9x7-trng
27 - const: microchip,sam9x60-trng
51 compatible = "atmel,at91sam9g45-trng";
H A Darm-cctrng.yaml7 title: Arm TrustZone CryptoCell TRNG engine
13 Arm TrustZone CryptoCell TRNG (True Random Number Generator) engine.
18 - arm,cryptocell-713-trng
19 - arm,cryptocell-703-trng
29 Arm TrustZone CryptoCell TRNG engine has 4 ring oscillators.
48 compatible = "arm,cryptocell-713-trng";
H A Dstarfive,jh7110-trng.yaml4 $id: http://devicetree.org/schemas/rng/starfive,jh7110-trng.yaml#
7 title: StarFive SoC TRNG Module
16 - const: starfive,jh8100-trng
17 - const: starfive,jh7110-trng
18 - const: starfive,jh7110-trng
52 compatible = "starfive,jh7110-trng";
H A Dsamsung,exynos5250-trng.yaml4 $id: http://devicetree.org/schemas/rng/samsung,exynos5250-trng.yaml#
16 - samsung,exynos5250-trng
17 - samsung,exynos850-trng
41 const: samsung,exynos850-trng
72 compatible = "samsung,exynos5250-trng";
H A Dxiphera,xip8001b-trng.yaml4 $id: http://devicetree.org/schemas/rng/xiphera,xip8001b-trng.yaml#
7 title: Xiphera XIP8001B-trng
17 const: xiphera,xip8001b-trng
31 compatible = "xiphera,xip8001b-trng";
H A Drockchip,rk3568-rng.yaml7 title: Rockchip RK3568 TRNG
25 - description: TRNG clock
26 - description: TRNG AHB clock
H A Dingenic,trng.yaml4 $id: http://devicetree.org/schemas/rng/ingenic,trng.yaml#
37 dtrng: trng@10072000 {
/linux/Documentation/devicetree/bindings/crypto/
H A Dqcom,prng.yaml20 - qcom,sa8255p-trng
21 - qcom,sa8775p-trng
22 - qcom,sc7280-trng
23 - qcom,sm8450-trng
24 - qcom,sm8550-trng
25 - qcom,sm8650-trng
26 - const: qcom,trng
48 const: qcom,trng
/linux/drivers/crypto/gemini/
H A Dsl3516-ce-rng.c20 ce = container_of(rng, struct sl3516_ce_dev, trng); in sl3516_ce_rng_read()
48 ce->trng.name = "SL3516 Crypto Engine RNG"; in sl3516_ce_rng_register()
49 ce->trng.read = sl3516_ce_rng_read; in sl3516_ce_rng_register()
50 ce->trng.quality = 700; in sl3516_ce_rng_register()
52 ret = hwrng_register(&ce->trng); in sl3516_ce_rng_register()
60 hwrng_unregister(&ce->trng); in sl3516_ce_rng_unregister()

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