| /linux/arch/arm64/boot/dts/exynos/ |
| H A D | exynos5433-tm2.dts | 3 * Samsung Exynos5433 TM2 board device tree source
7 * Device tree source file for Samsung's TM2 board which is based on
11 #include "exynos5433-tm2-common.dtsi"
14 model = "Samsung TM2 board";
15 compatible = "samsung,tm2", "samsung,exynos5433";
21 * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
70 compatible = "cypress,tm2-touchkey";
|
| H A D | exynos5433-tm2e.dts | 7 * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
11 #include "exynos5433-tm2-common.dtsi"
21 * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
|
| H A D | exynos5433-tm2-common.dtsi | 3 * Samsung Exynos5433 TM2 board device tree source
7 * Common device tree source file for Samsung's TM2 and TM2E boards
121 compatible = "samsung,tm2-audio";
|
| /linux/Documentation/devicetree/bindings/input/ |
| H A D | cypress,tm2-touchkey.yaml | 4 $id: http://devicetree.org/schemas/input/cypress,tm2-touchkey.yaml#
7 title: Samsung TM2 touch key controller
13 Touch key controllers similar to the TM2 can be found in a wide range of
23 - cypress,tm2-touchkey
65 compatible = "cypress,tm2-touchkey";
|
| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | samsung,tm2.yaml | 4 $id: http://devicetree.org/schemas/sound/samsung,tm2.yaml#
7 title: Samsung Exynos5433 TM2(E) audio complex with WM5110 codec
18 const: samsung,tm2-audio
70 compatible = "samsung,tm2-audio";
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | mediatek,mt8196-pinctrl.yaml | 36 - description: tm2 group IO
60 - const: tm2
220 "lb2", "tm1", "tm2", "tm3", "eint0", "eint1",
|
| /linux/sound/soc/samsung/ |
| H A D | Makefile | 27 snd-soc-tm2-wm5110-y := tm2_wm5110.o
42 obj-$(CONFIG_SND_SOC_SAMSUNG_TM2_WM5110) += snd-soc-tm2-wm5110.o
|
| H A D | Kconfig | 119 tristate "SoC I2S Audio support for WM5110 on TM2 board"
126 Say Y if you want to add support for SoC audio on the TM2 board.
|
| /linux/fs/btrfs/ |
| H A D | tree-mod-log.c | 1053 struct tree_mod_elem *tm2; in btrfs_get_old_root() local
1067 tm2 = tree_mod_log_search(fs_info, logical, time_seq); in btrfs_get_old_root()
1070 ASSERT(tm2); in btrfs_get_old_root()
1071 ASSERT(tm2 == tm || tm2->seq > tm->seq); in btrfs_get_old_root()
1072 if (!tm2 || tm2->seq < tm->seq) { in btrfs_get_old_root()
1076 tm = tm2; in btrfs_get_old_root()
|
| /linux/drivers/input/keyboard/ |
| H A D | tm2-touchkey.c | 3 * TM2 touchkey device driver
25 #define TM2_TOUCHKEY_DEV_NAME "tm2-touchkey"
336 .compatible = "cypress,tm2-touchkey",
|
| /linux/lib/zstd/common/ |
| H A D | cpu.h | 107 C(tm2, 8)
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | pipeline.json | 287 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
296 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
304 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | pipeline.json | 287 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
296 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
304 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/knightslanding/ |
| H A D | pipeline.json | 181 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | pipeline.json | 344 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
353 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
361 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | pipeline.json | 379 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
404 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | pipeline.json | 218 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
253 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | pipeline.json | 388 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
413 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | pipeline.json | 228 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
263 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | pipeline.json | 228 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
263 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | pipeline.json | 748 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
802 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
822 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
839 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | pipeline.json | 212 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
229 "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
|
| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | pipeline.json | 212 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
229 "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
|
| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | pipeline.json | 212 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
229 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|
| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | pipeline.json | 212 …is event is not affected by core frequency changes (for example, P states, TM2 transitions) but ha…
229 … due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason th…
|