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/linux/mm/
H A D	mmu_gather.c	14 #include <asm/tlb.h> 18 static bool tlb_next_batch(struct mmu_gather tlb) in tlb_next_batch() argument 23 if (tlb->delayed_rmap && tlb->active != &tlb->local) in tlb_next_batch() 26 batch = tlb->active; in tlb_next_batch() 28 tlb->active = batch->next; in tlb_next_batch() 32 if (tlb->batch_count == MAX_GATHER_BATCH_COUNT) in tlb_next_batch() 39 tlb->batch_count++; in tlb_next_batch() 44 tlb->active->next = batch; in tlb_next_batch() 45 tlb->active = batch; in tlb_next_batch() 73 tlb_flush_rmaps - do pending rmap removals after we have flushed the TLB [all …]
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A D	tlb.json	4 …"BriefDescription": "This event counts operations that cause a TLB refill of the L1I TLB. See L1I_… 8 …"BriefDescription": "This event counts operations that cause a TLB refill of the L1D TLB. See L1D_… 12 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D TLB. See L1D_… 16 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I TLB. See L1I_… 20 …"BriefDescription": "This event counts operations that cause a TLB refill of the L2D TLB. See L2D_… 24 …"BriefDescription": "This event counts operations that cause a TLB access to the L2D TLB. See L2D_… 28 … "BriefDescription": "This event counts data TLB access with at least one translation table walk." 32 …"BriefDescription": "This event counts instruction TLB access with at least one translation table … 37 … "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 4KB page." 42 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 64KB page." [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A D	tlb.json	4 …TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved … 8 …TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolv… 12 …TLB accesses caused by any memory load or store operation. Note that load or store instructions ca… 16 …ublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in … 20 …ion": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 28 …TLB driven by a memory access. Note that partial translations that also cause a table walk are cou… 32 … L2 TLB driven by a memory access. Partial translations that also cause a table walk are counted. … 36 …TLB refills caused by memory read operations. If there are multiple misses in the TLB that are res… 40 …TLB refills caused by data side memory write operations. If there are multiple misses in the TLB t… [all …]
H A D	metrics.json	47 …"BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions e… 54 …s the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication o… 56 "ScaleUnit": "1per TLB access" 86 …"BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instruc… 93 … instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication o… 95 "ScaleUnit": "1per TLB access" 114 …1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indicat… 116 "ScaleUnit": "1per TLB access" 121 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… 142 …TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indicat… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	tlb.json	4 …TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved … 8 …TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolv… 12 …TLB accesses caused by any memory load or store operation. Note that load or store instructions ca… 16 …ublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in … 20 …ion": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 28 …TLB driven by a memory access. Note that partial translations that also cause a table walk are cou… 32 … L2 TLB driven by a memory access. Partial translations that also cause a table walk are counted. … 36 …TLB refills caused by memory read operations. If there are multiple misses in the TLB that are res… 40 …TLB refills caused by data side memory write operations. If there are multiple misses in the TLB t… [all …]
H A D	metrics.json	40 …"BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions e… 47 …atio of instruction TLB Walks to the total number of data TLB accesses. This gives an indication o… 49 "ScaleUnit": "1per TLB access" 75 …"BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instruc… 82 … instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication o… 84 "ScaleUnit": "1per TLB access" 103 …1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indicat… 105 "ScaleUnit": "1per TLB access" 110 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… 131 …TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indicat… [all …]
/linux/arch/loongarch/include/asm/
H A D	tlb.h	`13 * TLB Invalidate Flush 26 * TLB R/W operations. 49 /* Invalid all tlb / 51 / Invalid current tlb / 53 / Invalid all global=1 lines in current tlb / 55 / Invalid all global=0 lines in current tlb / 57 / Invalid global=0 and matched asid lines in current tlb / 59 / Invalid addr with global=0 and matched asid in current tlb / 61 / Invalid addr with global=1 or matched asid in current tlb / 63 / Invalid matched gid in guest tlb */ [all …]`
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	translation.json	5 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G", 11 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M", 17 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K", 23 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K", 29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data… 47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc… 53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… 59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	mmu.json	9 "PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry", 12 "BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry" 15 "PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry", 18 "BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry" 21 "PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry", 24 "BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry" 27 "PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry", 30 "BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry" 33 "PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry", 36 "BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry" [all …]
/linux/arch/mips/kvm/
H A D	tlb.c	6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that 7 * TLB handlers run from KSEG0 26 #include <asm/tlb.h> 92 * Sets the root GuestID to match the current guest GuestID, for TLB operation 93 * on the GPA->RPA mappings in the root TLB. 96 * possibly longer if TLB registers are modified. 121 /* Set root GuestID for root probe and write of guest TLB entry / in kvm_vz_host_tlb_inv() 137 We don't want to get reserved instruction exceptions for missing tlb in kvm_vz_host_tlb_inv() 153 * kvm_vz_guest_tlb_lookup() - Lookup a guest VZ TLB mapping. 155 * @gpa: Guest virtual address in a TLB mapped guest segment. [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	virtual-memory.json	7 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 16 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 35 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 62 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 80 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 89 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	virtual-memory.json	7 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 16 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 35 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 62 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 80 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 89 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	virtual-memory.json	7 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 16 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 35 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 62 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 80 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 89 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 26 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 35 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 71 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 90 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 99 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 26 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 35 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 71 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 90 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 99 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 26 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 35 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 71 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 90 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 99 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 26 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 35 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 71 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 90 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 99 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A D	cache.json	129 "PublicDescription": "Level 1 PLD TLB refill", 132 "BriefDescription": "Level 1 PLD TLB refill" 135 …"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwa… 138 …"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwar… 141 "PublicDescription": "Level 1 TLB flush", 144 "BriefDescription": "Level 1 TLB flush" 147 "PublicDescription": "Level 2 TLB access", 150 "BriefDescription": "Level 2 TLB access" 153 …eload TLB access. This event only counts software and hardware prefetches at Level 1. This event c… 156 …eload TLB access. This event only counts software and hardware prefetches at Level 1. This event c… [all …]
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	virtual-memory.json	7 "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", 22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", 26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 35 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 44 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 53 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 71 "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 "BriefDescription": "Store misses in all TLB level [all...]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	virtual-memory.json	7 "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", 22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", 26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 35 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 44 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 53 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 71 "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 "BriefDescription": "Store misses in all TLB level [all...]
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	virtual-memory.json	7 "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", 22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", 26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 35 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 44 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 53 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 71 "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 "BriefDescription": "Store misses in all TLB level [all...]
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 28 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 38 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 48 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 58 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 68 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 88 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 109 …res whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 115 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… [all …]
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A D	virtual-memory.json	12 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 25 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 46 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 52 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 56 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 66 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 76 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 86 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 111 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor… 115 …"PublicDescription": "Counts the number of first level TLB misses but second level hits due to a d… [all …]
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 16 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 42 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 46 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 56 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 66 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 76 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 86 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 96 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 122 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor… [all …]
/linux/Documentation/arch/x86/
H A D	tlb.rst	4 The TLB 10 1. Flush the entire TLB with a two-instruction sequence. This is 11 a quick operation, but it causes collateral damage: TLB entries 17 damage to other TLB entries. 23 entire TLB than doing 2^48/PAGE_SIZE individual flushes. 24 2. The contents of the TLB. If the TLB is empty, then there will 28 3. The size of the TLB. The larger the TLB, the more collateral 29 damage we do with a full flush. So, the larger the TLB, the 32 4. The microarchitecture. The TLB has become a multi-level 37 especially the contents of the TLB during a given flush. The [all …]

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