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/linux/include/asm-generic/
H A D	tlb.h	2 /* include/asm-generic/tlb.h 4 * Generic TLB shootdown code 35 * correct and efficient ordering of freeing pages and TLB invalidations. 40 * 2) TLB invalidate page 53 * Finish in particular will issue a (final) TLB invalidate and free 94 * tlb_flush_mmu_tlbonly() - does the TLB invalidate (and resets 97 * tlb_flush_mmu() - in addition to the above TLB invalidate, also frees 114 * flush the entire TLB irrespective of the range. For instance 133 * returns the smallest TLB entry size unmapped in this range. 146 * This might be useful if your architecture has size specific TLB 218 tlb_remove_table(tlb,page) global() argument 279 tlb_delay_rmap(tlb) global() argument 293 tlb_delay_rmap(tlb) global() argument 294 tlb_flush_rmaps(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_flush_rmaps() argument 362 __tlb_adjust_range(struct mmu_gather * tlb,unsigned long address,unsigned int range_size) __tlb_adjust_range() argument 370 __tlb_reset_range(struct mmu_gather * tlb) __tlb_reset_range() argument 404 tlb_flush(struct mmu_gather * tlb) tlb_flush() argument 418 tlb_flush(struct mmu_gather * tlb) tlb_flush() argument 437 tlb_update_vma_flags(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_update_vma_flags() argument 455 tlb_flush_mmu_tlbonly(struct mmu_gather * tlb) tlb_flush_mmu_tlbonly() argument 469 tlb_remove_page_size(struct mmu_gather * tlb,struct page * page,int page_size) tlb_remove_page_size() argument 476 __tlb_remove_page(struct mmu_gather * tlb,struct page * page,bool delay_rmap) __tlb_remove_page() argument 486 tlb_remove_page(struct mmu_gather * tlb,struct page * page) tlb_remove_page() argument 491 tlb_remove_ptdesc(struct mmu_gather * tlb,void * pt) tlb_remove_ptdesc() argument 497 tlb_remove_page_ptdesc(struct mmu_gather * tlb,struct ptdesc * pt) tlb_remove_page_ptdesc() argument 502 tlb_change_page_size(struct mmu_gather * tlb,unsigned int page_size) tlb_change_page_size() argument 515 tlb_get_unmap_shift(struct mmu_gather * tlb) tlb_get_unmap_shift() argument 529 tlb_get_unmap_size(struct mmu_gather * tlb) tlb_get_unmap_size() argument 539 tlb_start_vma(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_start_vma() argument 550 tlb_end_vma(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_end_vma() argument 574 tlb_flush_pte_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pte_range() argument 581 tlb_flush_pmd_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pmd_range() argument 588 tlb_flush_pud_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pud_range() argument 595 tlb_flush_p4d_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_p4d_range() argument 603 __tlb_remove_tlb_entry(struct mmu_gather * tlb,pte_t * ptep,unsigned long address) __tlb_remove_tlb_entry() argument 615 tlb_remove_tlb_entry(tlb,ptep,address) global() argument 628 tlb_remove_tlb_entries(struct mmu_gather * tlb,pte_t * ptep,unsigned int nr,unsigned long address) tlb_remove_tlb_entries() argument 641 tlb_remove_huge_tlb_entry(h,tlb,ptep,address) global() argument 660 __tlb_remove_pmd_tlb_entry(tlb,pmdp,address) global() argument 663 tlb_remove_pmd_tlb_entry(tlb,pmdp,address) global() argument 674 __tlb_remove_pud_tlb_entry(tlb,pudp,address) global() argument 677 tlb_remove_pud_tlb_entry(tlb,pudp,address) global() argument 702 pte_free_tlb(tlb,ptep,address) global() argument 711 pmd_free_tlb(tlb,pmdp,address) global() argument 720 pud_free_tlb(tlb,pudp,address) global() argument 729 p4d_free_tlb(tlb,pudp,address) global() argument [all...]
/linux/mm/
H A D	mmu_gather.c	14 #include <asm/tlb.h> 18 static bool tlb_next_batch(struct mmu_gather tlb) in tlb_next_batch() argument 23 if (tlb->delayed_rmap && tlb->active != &tlb->local) in tlb_next_batch() 26 batch = tlb->active; in tlb_next_batch() 28 tlb->active = batch->next; in tlb_next_batch() 32 if (tlb->batch_count == MAX_GATHER_BATCH_COUNT) in tlb_next_batch() 39 tlb->batch_count++; in tlb_next_batch() 44 tlb in tlb_next_batch() 82 tlb_flush_rmaps(struct mmu_gather tlb,struct vm_area_struct * vma) tlb_flush_rmaps() argument 144 tlb_batch_pages_flush(struct mmu_gather * tlb) tlb_batch_pages_flush() argument 153 tlb_batch_list_free(struct mmu_gather * tlb) tlb_batch_list_free() argument 164 __tlb_remove_folio_pages_size(struct mmu_gather * tlb,struct page * page,unsigned int nr_pages,bool delay_rmap,int page_size) __tlb_remove_folio_pages_size() argument 205 __tlb_remove_folio_pages(struct mmu_gather * tlb,struct page * page,unsigned int nr_pages,bool delay_rmap) __tlb_remove_folio_pages() argument 212 __tlb_remove_page_size(struct mmu_gather * tlb,struct page * page,bool delay_rmap,int page_size) __tlb_remove_page_size() argument 302 tlb_table_invalidate(struct mmu_gather * tlb) tlb_table_invalidate() argument 320 tlb_table_flush(struct mmu_gather * tlb) tlb_table_flush() argument 331 tlb_remove_table(struct mmu_gather * tlb,void * table) tlb_remove_table() argument 350 tlb_table_init(struct mmu_gather * tlb) tlb_table_init() argument 357 tlb_table_flush(struct mmu_gather * tlb) tlb_table_flush() argument 358 tlb_table_init(struct mmu_gather * tlb) tlb_table_init() argument 362 tlb_flush_mmu_free(struct mmu_gather * tlb) tlb_flush_mmu_free() argument 370 tlb_flush_mmu(struct mmu_gather * tlb) tlb_flush_mmu() argument 376 __tlb_gather_mmu(struct mmu_gather * tlb,struct mm_struct * mm,bool fullmm) __tlb_gather_mmu() argument 409 tlb_gather_mmu(struct mmu_gather * tlb,struct mm_struct * mm) tlb_gather_mmu() argument 425 tlb_gather_mmu_fullmm(struct mmu_gather * tlb,struct mm_struct * mm) tlb_gather_mmu_fullmm() argument 437 tlb_finish_mmu(struct mmu_gather * tlb) tlb_finish_mmu() argument [all...]
/linux/arch/arm64/include/asm/
H A D	tlb.h	3 * Based on arch/arm/include/asm/tlb.h 15 static void tlb_flush(struct mmu_gather tlb); in __tlb_remove_table() 17 #include <asm-generic/tlb.h> in __tlb_remove_table() 24 static inline int tlb_get_level(struct mmu_gather tlb) 27 if (tlb->freed_tables) 30 if (tlb->cleared_ptes && !(tlb->cleared_pmds \|\| in tlb_get_level() 31 tlb->cleared_puds \|\| in tlb_get_level() 32 tlb->cleared_p4ds)) in tlb_get_level() 35 if (tlb in tlb_get_level() 29 tlb_get_level(struct mmu_gather * tlb) tlb_get_level() argument 58 tlb_flush(struct mmu_gather * tlb) tlb_flush() argument 80 __pte_free_tlb(struct mmu_gather * tlb,pgtable_t pte,unsigned long addr) __pte_free_tlb() argument 90 __pmd_free_tlb(struct mmu_gather * tlb,pmd_t * pmdp,unsigned long addr) __pmd_free_tlb() argument 101 __pud_free_tlb(struct mmu_gather * tlb,pud_t * pudp,unsigned long addr) __pud_free_tlb() argument [all...]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A D	tlb.json	4 …TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved … 8 …TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolv… 12 …TLB accesses caused by any memory load or store operation. Note that load or store instructions ca… 16 …ublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in … 20 …ion": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 28 …TLB driven by a memory access. Note that partial translations that also cause a table walk are cou… 32 … L2 TLB driven by a memory access. Partial translations that also cause a table walk are counted. … 36 …TLB refills caused by memory read operations. If there are multiple misses in the TLB that are res… 40 …TLB refills caused by data side memory write operations. If there are multiple misses in the TLB t… [all …]
H A D	metrics.json	47 …"BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions e… 54 …s the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication o… 56 "ScaleUnit": "1per TLB access" 86 …"BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instruc… 93 … instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication o… 95 "ScaleUnit": "1per TLB access" 114 …1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indicat… 116 "ScaleUnit": "1per TLB access" 121 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… 142 …TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indicat… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A D	tlb.json	4 "PublicDescription": "Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB." 8 "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction." 12 "PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operation. Note that load or store instructions can be broken up into multiple memory operations. This event does not count TLB maintenance operations." 16 "PublicDescription": "Counts level 1 instruction TLB accesse [all...]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	tlb.json	4 …TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved … 8 …TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolv… 12 …TLB accesses caused by any memory load or store operation. Note that load or store instructions ca… 16 …ublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in … 20 …ion": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 28 …TLB driven by a memory access. Note that partial translations that also cause a table walk are cou… 32 … L2 TLB driven by a memory access. Partial translations that also cause a table walk are counted. … 36 …TLB refills caused by memory read operations. If there are multiple misses in the TLB that are res… 40 …TLB refills caused by data side memory write operations. If there are multiple misses in the TLB t… [all …]
H A D	metrics.json	40 …"BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions e… 47 …atio of instruction TLB Walks to the total number of data TLB accesses. This gives an indication o… 49 "ScaleUnit": "1per TLB access" 75 …"BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instruc… 82 … instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication o… 84 "ScaleUnit": "1per TLB access" 103 …1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indicat… 105 "ScaleUnit": "1per TLB access" 110 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… 131 …TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indicat… [all …]
/linux/arch/loongarch/include/asm/
H A D	tlb.h	`13 * TLB Invalidate Flush 26 * TLB R/W operations. 49 /* Invalid all tlb / 51 / Invalid current tlb / 53 / Invalid all global=1 lines in current tlb / 55 / Invalid all global=0 lines in current tlb / 57 / Invalid global=0 and matched asid lines in current tlb / 59 / Invalid addr with global=0 and matched asid in current tlb / 61 / Invalid addr with global=1 or matched asid in current tlb / 63 / Invalid matched gid in guest tlb */ [all …]`
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	translation.json	5 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G", 11 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M", 17 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K", 23 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K", 29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data… 47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc… 53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… 59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	mmu.json	9 "PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry", 12 "BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry" 15 "PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry", 18 "BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry" 21 "PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry", 24 "BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry" 27 "PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry", 30 "BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry" 33 "PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry", 36 "BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry" [all …]
/linux/arch/riscv/include/asm/
H A D	tlb.h	`11 static void tlb_flush(struct mmu_gather tlb); 14 #include <asm-generic/tlb.h> 16 static inline void tlb_flush(struct mmu_gather tlb) 19 if (tlb->fullmm \|\| tlb->need_flush_all \|\| tlb->freed_tables) 20 flush_tlb_mm(tlb->mm); 22 flush_tlb_mm_range(tlb->mm, tlb->start, tlb 34 tlb_flush(struct mmu_gather * tlb) tlb_flush() argument [all...]`
/linux/arch/mips/kvm/
H A D	tlb.c	6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that 7 * TLB handlers run from KSEG0 26 #include <asm/tlb.h> 92 * Sets the root GuestID to match the current guest GuestID, for TLB operation 93 * on the GPA->RPA mappings in the root TLB. 96 * possibly longer if TLB registers are modified. 121 /* Set root GuestID for root probe and write of guest TLB entry / in kvm_vz_host_tlb_inv() 137 We don't want to get reserved instruction exceptions for missing tlb in kvm_vz_host_tlb_inv() 153 * kvm_vz_guest_tlb_lookup() - Lookup a guest VZ TLB mapping. 155 * @gpa: Guest virtual address in a TLB mapped guest segment. [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	virtual-memory.json	7 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 16 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 35 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 62 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 80 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 89 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	virtual-memory.json	7 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 16 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 35 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 62 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 80 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 89 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	virtual-memory.json	7 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 16 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 35 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 62 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 80 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 89 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… [all …]
/linux/drivers/gpu/drm/v3d/
H A D	v3d_perfmon.c	17 …{"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test… 18 …{"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and … 19 …{"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and ste… 20 {"TLB", "TLB-quads-with-zero-coverage", "[TLB] Quads with all pixels having zero coverage"}, 21 …{"TLB", "TLB-quads-with-non-zero-coverage", "[TLB] Quads with any pixels having non-zero coverage"… 22 …{"TLB", "TLB-quads-written-to-color-buffer", "[TLB] Quads with valid pixels written to colour buff… 61 …{"TLB", "TLB-partial-quads-written-to-color-buffer", "[TLB] Partial quads written to the colour bu… 87 {"TLB", "TLB-memory-writes", "[TLB] Total memory writes"}, 92 {"TLB", "TLB-memory-reads", "[TLB] Total memory reads"}, 95 {"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"}, [all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 26 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 35 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 71 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 90 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 99 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 26 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 35 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 71 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 90 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 99 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 26 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 35 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 71 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 90 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 99 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 26 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 35 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 53 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 71 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 90 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 99 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/linux/arch/arm/include/asm/
H A D	tlb.h	3 * arch/arm/include/asm/tlb.h 8 * to use the "invalidate whole tlb" rather than "invalidate single 9 * tlb" for this. 23 #define tlb_flush(tlb) ((void) tlb) argument 25 #include <asm-generic/tlb.h> 30 #include <asm-generic/tlb.h> 33 __pte_free_tlb(struct mmu_gather tlb, pgtable_t pte, unsigned long addr) in __tlb_remove_table() 43 __tlb_adjust_range(tlb, addr - PAGE_SIZE, 2 PAGE_SIZE); in __pte_free_tlb() 46 tlb_remove_ptdesc(tlb, ptdes in __pte_free_tlb() 40 __pte_free_tlb(struct mmu_gather * tlb,pgtable_t pte,unsigned long addr) __pte_free_tlb() argument 59 __pmd_free_tlb(struct mmu_gather * tlb,pmd_t * pmdp,unsigned long addr) __pmd_free_tlb() argument [all...]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A D	cache.json	129 "PublicDescription": "Level 1 PLD TLB refill", 132 "BriefDescription": "Level 1 PLD TLB refill" 135 …"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwa… 138 …"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwar… 141 "PublicDescription": "Level 1 TLB flush", 144 "BriefDescription": "Level 1 TLB flush" 147 "PublicDescription": "Level 2 TLB access", 150 "BriefDescription": "Level 2 TLB access" 153 …eload TLB access. This event only counts software and hardware prefetches at Level 1. This event c… 156 …eload TLB access. This event only counts software and hardware prefetches at Level 1. This event c… [all …]
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 26 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 35 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 62 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 77 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 81 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 90 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 99 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	virtual-memory.json	7 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 26 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 35 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 44 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 62 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 77 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 81 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 90 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to … 99 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to … [all …]

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