Searched full:tegra210_clk_pll_a_out0 (Results 1 – 6 of 6) sorted by relevance
76 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;80 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,82 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;102 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;172 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
140 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;177 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;188 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
94 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
110 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1512 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1525 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1538 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1551 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1564 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1632 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1644 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1656 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;2020 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;2024 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,[all …]
280 #define TEGRA210_CLK_PLL_A_OUT0 249 macro