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/linux/drivers/soc/qcom/
H A Drpmh-internal.h12 #include <soc/qcom/tcs.h>
23 * struct tcs_group: group of Trigger Command Sets (TCS) to send state requests
27 * @type: Type of the TCS in this group - active, sleep, wake.
29 * @offset: Start of the TCS group relative to the TCSes in the RSC.
31 * @ncpt: Number of commands in each TCS.
32 * @req: Requests that are sent from the TCS; only used for ACTIVE_ONLY
33 * transfers (could be on a wake/sleep TCS if we are borrowing for
42 * MAX_CMDS_PER_TCS = 16 then bit[2] = the first bit in 2nd TCS.
98 * @tcs_base: Start address of the TCS registers in this controller.
106 * @tcs: TCS groups.
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/linux/drivers/scsi/aic94xx/
H A Daic94xx_tmf.c47 #define DECLARE_TCS(tcs) \ argument
48 struct tasklet_completion_status tcs = { \
59 struct tasklet_completion_status *tcs = ascb->uldd_task; in asd_clear_nexus_tasklet_complete() local
66 tcs->dl_opcode = dl->opcode; in asd_clear_nexus_tasklet_complete()
74 struct tasklet_completion_status *tcs = ascb->uldd_task; in asd_clear_nexus_timedout() local
77 tcs->dl_opcode = TMF_RESP_FUNC_FAILED; in asd_clear_nexus_timedout()
86 DECLARE_TCS(tcs); \
95 ascb->uldd_task = &tcs; \
107 res = tcs.dl_opcode; \
248 struct tasklet_completion_status *tcs = ascb->uldd_task; in asd_tmf_timedout() local
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/linux/tools/testing/selftests/sgx/
H A Dtest_encl.c76 void *tcs = (void *)op->tcs_page; in do_encl_init_tcs_page() local
79 memset(tcs, 0, 16); /* STATE and FLAGS */ in do_encl_init_tcs_page()
80 memcpy(tcs + 16, &op->ssa, 8); /* OSSA */ in do_encl_init_tcs_page()
81 memset(tcs + 24, 0, 4); /* CSSA */ in do_encl_init_tcs_page()
83 memcpy(tcs + 28, &val_32, 4); /* NSSA */ in do_encl_init_tcs_page()
84 memcpy(tcs + 32, &op->entry, 8); /* OENTRY */ in do_encl_init_tcs_page()
85 memset(tcs + 40, 0, 24); /* AEP, OFSBASE, OGSBASE */ in do_encl_init_tcs_page()
87 memcpy(tcs + 64, &val_32, 4); /* FSLIMIT */ in do_encl_init_tcs_page()
88 memcpy(tcs + 68, &val_32, 4); /* GSLIMIT */ in do_encl_init_tcs_page()
89 memset(tcs + 72, 0, 4024); /* Reserved */ in do_encl_init_tcs_page()
H A Dmain.c134 * Return the offset in the enclave where the TCS segment can be found.
135 * The first RW segment loaded is the TCS.
153 * The first RW segment loaded is the TCS, skip that to get info on the
290 self->run.tcs = self->encl.encl_base; in TEST_F()
363 self->run.tcs = self->encl.encl_base; in TEST_F()
429 self->run.tcs = self->encl.encl_base;
512 self->run.tcs = self->encl.encl_base; in TEST_F()
548 self->run.tcs = self->encl.encl_base; in TEST_F()
572 * Sanity check that it is possible to enter either of the two hardcoded TCS
581 self->run.tcs = self->encl.encl_base; in TEST_F()
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H A Dtest_encl_bootstrap.S10 .section ".tcs", "aw"
43 # RBX contains the base address for TCS, which is the first address
44 # inside the enclave for TCS #1 and one page into the enclave for
45 # TCS #2. First make it relative by substracting __encl_base and
53 # Entry point for dynamically created TCS page expected to follow
87 # Stack of TCS #1
91 # Stack of TCS #2
H A Dtest_encl.lds5 tcs PT_LOAD;
14 .tcs : {
15 *(.tcs*)
16 } : tcs
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_lib.c25 u8 tcs = adapter->hw_tcs; in ixgbe_cache_ring_dcb_sriov() local
28 if (tcs <= 1) in ixgbe_cache_ring_dcb_sriov()
39 if ((reg_idx & ~vmdq->mask) >= tcs) { in ixgbe_cache_ring_dcb_sriov()
50 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
61 if (fcoe->offset < tcs) in ixgbe_cache_ring_dcb_sriov()
113 * TCs : TC0/1 TC2/3 TC4-7 in ixgbe_get_first_reg_idx()
126 * TCs : TC0 TC1 TC2/3 in ixgbe_get_first_reg_idx()
334 u8 tcs = adapter->hw_tcs; in ixgbe_set_dcb_sriov_queues() local
337 if (tcs <= 1) in ixgbe_set_dcb_sriov_queues()
345 vmdq_i = min_t(u16, vmdq_i, MAX_TX_QUEUES / tcs); in ixgbe_set_dcb_sriov_queues()
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H A Dixgbe_dcb_82599.c204 * So clear all TCs and only enable those that should be in ixgbe_dcb_config_pfc_82599()
257 /* Configure pause time (2 TCs per register) */ in ixgbe_dcb_config_pfc_82599()
295 * Tx queues are allocated non-uniformly to TCs: in ixgbe_dcb_config_tc_stats_82599()
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Diavf.rst155 1. Create traffic classes (TCs). Maximum of 8 TCs can be created per interface.
158 Example: Sets up two tcs, tc0 and tc1, with 16 queues each and max tx rate set
167 map: priority mapping for up to 16 priorities to tcs (e.g. map 0 0 0 0 1 1 1 1
172 number of queues for all tcs is 64 or number of cores, whichever is lower.)
176 TCs, the queue configurations, and the QoS parameters.
186 TCs are configured using mqprio.
192 3. Apply TCs to ingress (RX) flow of interface::
199 - Setting up channels via ethtool (ethtool -L) is not supported when the TCs
216 - If traffic matches multiple TC filters that point to different TCs, that
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dcb_lib.c9 * ice_dcb_get_ena_tc - return bitmap of enabled TCs
10 * @dcbcfg: DCB config to evaluate for enabled TCs
103 * ice_dcb_get_num_tc - Get the number of TCs from DCBX config
104 * @dcbcfg: config to retrieve number of TCs from
114 * enabled and create a bitmask of enabled TCs in ice_dcb_get_num_tc()
119 /* Scan bitmask for contiguous TCs starting with TC0 */ in ice_dcb_get_num_tc()
125 pr_err("Non-contiguous TCs - Disabling DCB\n"); in ice_dcb_get_num_tc()
158 /* get bitmap of enabled TCs */ in ice_get_first_droptc()
161 /* get bitmap of PFC enabled TCs */ in ice_get_first_droptc()
318 /* returns number of contigous TCs and 1 TC for non-contigous TCs, in ice_dcb_bwchk()
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/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2.c115 unsigned int tcs, q_per_tc; in hw_atl2_hw_queue_to_tc_map_set() local
124 tcs = 8; in hw_atl2_hw_queue_to_tc_map_set()
128 tcs = 4; in hw_atl2_hw_queue_to_tc_map_set()
135 for (tc = 0; tc != tcs; tc++) { in hw_atl2_hw_queue_to_tc_map_set()
177 tx_buff_size /= cfg->tcs; in hw_atl2_hw_qos_set()
178 rx_buff_size /= cfg->tcs; in hw_atl2_hw_qos_set()
179 for (tc = 0; tc < cfg->tcs; tc++) { in hw_atl2_hw_qos_set()
263 (BIT(nic_cfg->tcs) - 1); in hw_atl2_hw_init_tx_tc_rate_limit()
269 for (tc = 0; tc != nic_cfg->tcs; tc++) { in hw_atl2_hw_init_tx_tc_rate_limit()
295 for (tc = 0; tc != nic_cfg->tcs; tc++) { in hw_atl2_hw_init_tx_tc_rate_limit()
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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,bcm-voter.yaml24 qcom,tcs-wait:
30 The AMC TCS is triggered immediately when icc_set_bw() is called. The
63 qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
/linux/drivers/net/ethernet/mscc/
H A Docelot_mm.c60 /* Only commit preemptible TCs when MAC Merge is active. in ocelot_port_update_active_preemptible_tcs()
71 * TCs affects the oversized frame dropping logic, so that needs to be in ocelot_port_update_active_preemptible_tcs()
79 "port %d %s/%s, MM TX %s, preemptible TCs 0x%x, active 0x%x\n", in ocelot_port_update_active_preemptible_tcs()
/linux/drivers/interconnect/qcom/
H A Dbcm-voter.c14 #include <soc/qcom/tcs.h>
30 * @tcs_wait: mask for which buckets require TCS completion
265 * qcom_icc_bcm_voter_commit - generates and commits tcs cmds based on bcms
382 if (of_property_read_u32(np, "qcom,tcs-wait", &voter->tcs_wait)) in qcom_icc_bcm_voter_probe()
H A Dbcm-voter.h11 #include <soc/qcom/tcs.h>
/linux/arch/x86/kernel/cpu/sgx/
H A Dioctl.c385 * A SECINFO for a TCS is required to always contain zero permissions because
394 * 2. A TCS page: PROT_R | PROT_W.
912 * or SGX_PAGE_TYPE_TRIM but TCS pages can only be trimmed. in sgx_enclave_modify_types()
925 * Once a regular page becomes a TCS page it cannot be in sgx_enclave_modify_types()
927 * the TCS page that is always RW from kernel perspective but in sgx_enclave_modify_types()
1016 * * It is possible to add TCS pages to an enclave by changing the type of
1017 * regular pages (%SGX_PAGE_TYPE_REG) to TCS (%SGX_PAGE_TYPE_TCS) pages.
1021 * * Regular or TCS pages can dynamically be removed from an initialized
/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_dcbnl.c15 /* we support 8 TCs in all modes */ in fm10k_dcbnl_ieee_getets()
81 /* record flow control max count and state of TCs */ in fm10k_dcbnl_ieee_getpfc()
/linux/drivers/net/ethernet/broadcom/bnge/
H A Dbnge_resc.c17 u16 tcs = bd->num_tc; in bnge_num_tx_to_cp() local
19 if (!tcs) in bnge_num_tx_to_cp()
20 tcs = 1; in bnge_num_tx_to_cp()
22 return tx / tcs; in bnge_num_tx_to_cp()
/linux/drivers/net/ethernet/aquantia/atlantic/
H A Daq_nic.h73 u8 tcs; member
216 int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map);
H A Daq_filters.c175 if (fsp->ring_cookie > cfg->num_rss_queues * cfg->tcs) { in aq_check_approve_fvlan()
178 cfg->num_rss_queues * cfg->tcs - 1); in aq_check_approve_fvlan()
280 if (fsp->ring_cookie >= cfg->num_rss_queues * cfg->tcs) { in aq_rule_is_not_correct()
284 cfg->num_rss_queues * cfg->tcs - 1); in aq_rule_is_not_correct()
/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dsharedbuffer_configuration.py78 # Multicast TCs cannot be changed
113 # Multicast TCs cannot be changed
296 # Bind each port and unicast TC (TCs < 8) to a random pool and a random
/linux/arch/mips/include/asm/
H A Dmips_mt.h12 * How many VPEs and TCs is Linux allowed to use? 0 means no limit.
/linux/drivers/gpib/tms9914/
H A Dtms9914.c57 * The agilent 82350B has a buggy implementation of tcs which interferes with the
60 * manual describes tcs as putting the controller into a CWAS
62 * functioning tca is far more important than tcs, we work around the
63 * problem by never issuing tcs.
68 * directly (which does issue tcs).
/linux/include/soc/qcom/
H A Drpmh.h9 #include <soc/qcom/tcs.h>
/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_b0.c172 tx_buff_size /= cfg->tcs; in hw_atl_b0_hw_qos_set()
173 rx_buff_size /= cfg->tcs; in hw_atl_b0_hw_qos_set()
174 for (tc = 0; tc < cfg->tcs; tc++) { in hw_atl_b0_hw_qos_set()
353 (BIT(nic_cfg->tcs) - 1); in hw_atl_b0_hw_init_tx_tc_rate_limit()
359 for (tc = 0; tc != nic_cfg->tcs; tc++) { in hw_atl_b0_hw_init_tx_tc_rate_limit()
390 for (tc = 0; tc != nic_cfg->tcs; tc++) { in hw_atl_b0_hw_init_tx_tc_rate_limit()
404 (nic_cfg->tcs - num_min_rated_tcs); in hw_atl_b0_hw_init_tx_tc_rate_limit()
438 for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) { in hw_atl_b0_hw_init_tx_tc_rate_limit()

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