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/linux/drivers/thermal/intel/
H A Dintel_tcc.c3 * intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access
15 * @tcc_offset: TCC offset in MSR_TEMPERATURE_TARGET
141 * intel_tcc_get_offset_mask() - Returns the bitmask to read TCC offset
145 * not support TCC offset.
147 * Return: The model-specific bitmask for TCC offset.
174 * intel_tcc_get_tjmax() - returns the default TCC activation Temperature
177 * Get the TjMax value, which is the default thermal throttling or TCC
201 * intel_tcc_get_offset() - returns the TCC Offset value to Tjmax
204 * Get the TCC offset value to Tjmax. The effective thermal throttling or TCC
205 * activation temperature equals "Tjmax" - "TCC Offset", in degrees C.
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H A Dintel_tcc_cooling.c4 * programming the TCC Offset register.
96 pr_info("TCC Offset locked\n"); in tcc_cooling_init()
100 pr_info("Programmable TCC Offset detected\n"); in tcc_cooling_init()
103 thermal_cooling_device_register("TCC Offset", NULL, in tcc_cooling_init()
122 MODULE_DESCRIPTION("TCC offset cooling device Driver");
H A DKconfig93 tristate "Intel TCC offset cooling Driver"
97 Enable this to support system cooling by adjusting the effective TCC
98 activation temperature via the TCC Offset register, which is widely
/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,mdp3-tcc.yaml4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
13 Tone Curve Conversion (TCC) is one of Media Profile Path 3 (MDP3) components.
21 - mediatek,mt8195-mdp3-tcc
58 compatible = "mediatek,mt8195-mdp3-tcc";
/linux/arch/parisc/net/
H A Dbpf_jit_comp64.c225 /* exit point is either at next instruction, or the outest TCC exit function */ in __build_epilogue()
239 /* load original return pointer (stored by outest TCC function) */ in __build_epilogue()
358 /* get address of TCC main exit function for error case into rp */ in emit_bpf_tail_call()
374 * if (--tcc < 0) in emit_bpf_tail_call()
396 * tcc = temp_tcc; in emit_bpf_tail_call()
475 /* Backup TCC. */ in emit_call()
495 /* Restore TCC. */ in emit_call()
1121 * The first 4 words initialize the TCC and compares them. in bpf_jit_build_prologue()
1125 * The first instruction sets the tail-call-counter (TCC) register. in bpf_jit_build_prologue()
1179 * Now really set the tail call counter (TCC) register. in bpf_jit_build_prologue()
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H A Dbpf_jit_comp32.c198 /* exit point is either directly below, or the outest TCC exit function */ in __build_epilogue()
212 /* load original return pointer (stored by outest TCC function) */ in __build_epilogue()
917 /* backup TCC */ in emit_call()
931 /* restore TCC */ in emit_call()
956 /* get address of TCC main exit function for error case into rp */ in emit_bpf_tail_call()
972 * if (--tcc < 0) in emit_bpf_tail_call()
994 * tcc = temp_tcc; in emit_bpf_tail_call()
1496 * The first instruction sets the tail-call-counter (TCC) register. in bpf_jit_build_prologue()
1529 * now really set the tail call counter (TCC) register. in bpf_jit_build_prologue()
1535 * save epilogue function pointer for outer TCC call chain. in bpf_jit_build_prologue()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ras.h225 /* TCC (5 sub-ranges) */
227 /* TCC range 0 */
241 /* TCC range 1 */
248 /* TCC range 2 */
261 /* TCC range 3 */
268 /* TCC range 4 */
H A Dumc_v8_7.c86 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
297 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v8_7_querry_uncorrectable_error_count()
H A Dumc_v12_0.c76 "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, PCC:%llu, UC:%llu, TCC:%llu\n", in umc_v12_0_is_deferred_error()
83 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) in umc_v12_0_is_deferred_error()
99 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)); in umc_v12_0_is_uncorrectable_error()
H A Dumc_v8_10.c139 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v8_10_query_uncorrectable_error_count()
374 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) { in umc_v8_10_ecc_info_query_uncorrectable_error_count()
H A Dumc_v6_7.c156 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) { in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
354 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) { in umc_v6_7_querry_uncorrectable_error_count()
H A Dumc_v6_1.c250 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v6_1_querry_uncorrectable_error_count()
/linux/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_device.c152 unsigned int tcc; in tcc_offset_degree_celsius_store() local
163 if (kstrtouint(buf, 0, &tcc)) in tcc_offset_degree_celsius_store()
166 err = intel_tcc_set_offset(-1, tcc); in tcc_offset_degree_celsius_store()
/linux/include/linux/
H A Dintel_tcc.h3 * header for Intel TCC (thermal control circuitry) library
/linux/arch/mips/net/
H A Dbpf_jit_comp64.c481 u8 tcc = bpf2mips64[JIT_REG_TC]; in emit_tail_call() local
500 /* if (--TCC < 0) goto out */ in emit_tail_call()
501 emit(ctx, daddiu, tcc, tcc, -1); /* tcc-- (delay slot) */ in emit_tail_call()
502 emit(ctx, bltz, tcc, get_offset(ctx, 1)); /* PC += off(1) if tcc < 0 */ in emit_tail_call()
554 * In the unlikely event that the TCC limit is raised to more in build_prologue()
/linux/tools/net/ynl/samples/
H A DMakefile24 @echo -e '\tCC sample $@'
/linux/arch/loongarch/net/
H A Dbpf_jit.c102 * First instruction initializes the tail call count (TCC). in build_prologue()
103 * On tail call we skip this instruction, and the TCC is in build_prologue()
188 * of TCC initialization. in __build_epilogue()
214 u8 tcc = tail_call_reg(ctx); in emit_bpf_tail_call() local
240 * if (--TCC < 0) in emit_bpf_tail_call()
243 emit_insn(ctx, addid, REG_TCC, tcc, -1); in emit_bpf_tail_call()
/linux/tools/net/ynl/generated/
H A DMakefile40 @echo -e "\tCC $@"
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_sm_mt8195.h269 struct mdp_tcc_data_8195 tcc; member
/linux/tools/power/x86/turbostat/
H A Dturbostat.8128 …TCC temperature\fP sets the Thermal Control Circuit temperature for systems which do not export th…
279 cpu7: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT PREFETCH TURBO)
/linux/drivers/video/fbdev/
H A Dimsttfb.c585 __u8 tcc, mxc, lckl_n, mic; in set_imstt_regvals_tvp() local
591 tcc = 0x80; in set_imstt_regvals_tvp()
598 tcc = 0x44; in set_imstt_regvals_tvp()
605 tcc = 0x5e; in set_imstt_regvals_tvp()
612 tcc = 0x46; in set_imstt_regvals_tvp()
631 par->cmap_regs[TVPIDATA] = tcc; eieio(); in set_imstt_regvals_tvp()
/linux/arch/riscv/net/
H A Dbpf_jit_comp32.c754 /* Backup TCC. */ in emit_call()
765 /* Restore TCC. */ in emit_call()
802 * if (--tcc < 0) in emit_bpf_tail_call()
823 * tcc = temp_tcc; in emit_bpf_tail_call()
1321 * The first instruction sets the tail-call-counter (TCC) register. in bpf_jit_build_prologue()
H A Dbpf_jit_comp64.c275 /* kcfi, fentry and TCC init insns will be skipped on tailcall */ in __build_epilogue()
358 u8 tcc = rv_tail_call_reg(ctx); in emit_bpf_tail_call() local
378 /* if (--TCC < 0) in emit_bpf_tail_call()
381 emit_addi(RV_REG_TCC, tcc, -1, ctx); in emit_bpf_tail_call()
2051 * (TCC) register. This instruction is skipped for tail calls. in bpf_jit_build_prologue()
/linux/arch/x86/net/
H A Dbpf_jit_comp32.c1207 const u8 *tcc = bpf2ia32[TCALL_CNT]; in emit_prologue() local
1237 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[0])); in emit_prologue()
1238 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1])); in emit_prologue()
1306 const u8 *tcc = bpf2ia32[TCALL_CNT]; in emit_bpf_tail_call() local
1331 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0])); in emit_bpf_tail_call()
1332 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1])); in emit_bpf_tail_call()
1349 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0])); in emit_bpf_tail_call()
1351 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1])); in emit_bpf_tail_call()
/linux/arch/arm/net/
H A Dbpf_jit_32.c1401 const s8 *tcc = bpf2a32[TCALL_CNT]; in emit_bpf_tail_call() local
1434 tc = arm_bpf_get_reg64(tcc, tmp, ctx); in emit_bpf_tail_call()
1440 arm_bpf_put_reg64(tcc, tmp, ctx); in emit_bpf_tail_call()
1530 const s8 *tcc = bpf2a32[TCALL_CNT]; in build_prologue() local
1557 emit_a32_mov_r64(true, tcc, bpf_r1, ctx); in build_prologue()

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