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/freebsd/usr.sbin/cxgbetool/
H A Dcxgbetool.840 .Bl -item -compact
47 .Nm Ar nexus Cm clip Bro Cm hold | release Brc Ar ipv6-address
55 .Nm Ar nexus Cm hashfilter Ar filter-specification
63 .Nm Ar nexus Cm filter Ar idx Ar filter-specification
71 .Nm Ar nexus Cm loadcfg Ar fw-config.txt
75 .Nm Ar nexus Cm loadfw Ar fw-image.bin
85 .Nm Ar nexus Cm regdump Op Ar register-block ...
87 .Nm Ar nexus Cm sched-class Ar sub-command Op Ar param Ar value
89 .Nm Ar nexus Cm sched-queue Ar port Ar queue Ar class
97 provides command-line access to features and debug facilities exported by
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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/freebsd/sys/dev/cxgbe/firmware/
H A Dt5fw_cfg_fpga.txt3 # Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
27 # Virtual Functions based off of a Physical Function all get the
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
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H A Dt4fw_cfg_uwire.txt3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
27 # Virtual Functions based off of a Physical Function all get the
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
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H A Dt6fw_cfg_fpga.txt3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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H A Dt5fw_cfg_uwire.txt3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 4-port T5-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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H A Dt6fw_cfg_uwire.txt3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmicrochip,sparx5-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
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/freebsd/sys/dev/ice/
H A Dice_flex_pipe.c1 /* SPDX-License-Identifier: BSD-3-Clause */
112 * ice_sect_id - returns section ID
132 if (hw->tnl.count < ICE_TUNNEL_MAX_ENTRIES) { in ice_add_tunnel_hint()
143 * character ('0' - '7') will be located where our in ice_add_tunnel_hint()
146 if ((label_name[len] - '0') == hw->pf_id) { in ice_add_tunnel_hint()
147 hw->tn in ice_add_tunnel_hint()
2446 u16 tcam = 0; ice_upd_prof_hw() local
3128 ice_prof_tcam_ena_dis(struct ice_hw * hw,enum ice_block blk,bool enable,u16 vsig,struct ice_tcam_inf * tcam,struct LIST_HEAD_TYPE * chg) ice_prof_tcam_ena_dis() argument
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H A Dice_ddp_common.c1 /* SPDX-License-Identifier: BSD-3-Clause */
68 cmd->flags |= ICE_AQC_DOWNLOAD_PKG_LAST_BUF; in ice_aq_download_pkg()
77 *error_offset = LE32_TO_CPU(resp->error_offset); in ice_aq_download_pkg()
79 *error_info = LE32_TO_CPU(resp->error_info); in ice_aq_download_pkg()
137 cmd->flags |= ICE_AQC_DOWNLOAD_PKG_LAST_BUF; in ice_aq_update_pkg()
146 *error_offset = LE32_TO_CPU(resp->error_offset); in ice_aq_update_pkg()
148 *error_info = LE32_TO_CPU(resp->error_inf in ice_aq_update_pkg()
2200 struct ice_boost_tcam_entry *tcam; ice_find_boost_entry() local
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dinterlaken-lac.txt2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
7 - Example LAC Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
10 - Example LAC SWP Node with Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
17 The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
18 facilitate interoperability between a data path device and a look-aside
19 co-processor, the Interlaken Look-Aside protocol is defined for short
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/freebsd/sys/dev/cxgbe/common/
H A Dt4_hw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
49 * t4_wait_op_done_val - wait until an operation is completed
52 * @mask: a single-bit field within @reg that indicates completion
61 * operation completes and -EAGAIN otherwise.
74 if (--attempts == 0) in t4_wait_op_done_val()
75 return -EAGAIN; in t4_wait_op_done_val()
89 * t4_set_reg_field - set a register field to a value
108 * t4_read_indirect - read indirectly addressed registers
123 while (nregs--) { in t4_read_indirect()
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/freebsd/sys/dev/bnxt/bnxt_en/
H A Dhsi_struct_def.h1 /*-
34 * Copyright(c) 2001-2024, Broadcom. All rights reserved. The
71 * * 0x0-0xFFF8 - The function ID
72 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
73 * * 0xFFFD - Reserved for user-space HWRM interface
74 * * 0xFFFF - HWRM
122 /* Engine CKV - The Alias key EC curve and ECC public key information. */
124 /* Engine CKV - Initialization vector. */
126 /* Engine CKV - Authentication tag. */
128 /* Engine CKV - The encrypted data. */
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/freebsd/sys/dev/cxgb/
H A Dcxgb_main.c2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
151 {PCI_VENDOR_ID_CHELSIO, 0x0036, 3, "S320E-CR"},
152 {PCI_VENDOR_ID_CHELSIO, 0x0037, 7, "N320E-G2"},
174 nitems(cxgb_identifiers) - 1);
226 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
238 "MSI-X, MSI, INTx selector");
241 * The driver uses an auto-queue algorithm by default.
242 * To disable it and force a single queue-set per port, use multiq = 0
246 "use min(ncpus/ports, 8) queue-sets per port");
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright © 2021-2023 Dmitry Salychev
35 * high-functioning network interface. The DPNI supports features that are
112 mtx_assert(&(__sc)->lock, MA_NOTOWNED); \
113 mtx_lock(&(__sc)->lock); \
116 mtx_assert(&(__sc)->lock, MA_OWNED); \
117 mtx_unlock(&(__sc)->lock); \
120 mtx_assert(&(__sc)->lock, MA_OWNED); \
124 (&(sc)->channels[(chan)]->txc_queue.tx_rings[(tc)])
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/freebsd/sys/dev/cxgbe/
H A Dt4_main.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
270 * Each tunable is set to a default value here if it's known at compile-time.
271 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
288 int t4_ntxq = -NTXQ;
294 int t4_nrxq = -NRXQ;
300 static int t4_ntxq_vi = -NTXQ_VI;
305 static int t4_nrxq_vi = -NRXQ_VI;
311 0, "Reserve TX queue 0 of each VI for non-flowid packets");
315 static int t4_nofldtxq = -NOFLDTXQ;
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