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/linux/Documentation/devicetree/bindings/clock/
H A Dmarvell,armada-3700-uart-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Pali Rohár <pali@kernel.org>
13 const: marvell,armada-3700-uart-clock
17 - description: UART Clock Control Register
18 - description: UART 2 Baud Rate Divisor Register
23 "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
26 It is suggest to specify at least one TBG clock to achieve
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/linux/drivers/clk/mvebu/
H A Darmada-37xx-tbg.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 #include <linux/clk-provider.h>
47 static const struct tbg_def tbg[NUM_TBG] = { variable
48 {"TBG-A-P", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL8, TBG_A_VCODIV_DIFF},
49 {"TBG-B-P", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL8, TBG_B_VCODIV_DIFF},
50 {"TBG-A-S", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL1, TBG_A_VCODIV_SE},
51 {"TBG-B-S", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL1, TBG_B_VCODIV_SE},
60 return ((val >> ptbg->fbdiv_offset) & TBG_DIV_MASK) << 2; in tbg_get_mult()
70 div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK; in tbg_get_div()
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H A Darmada-37xx-periph.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * TBG-A-P --| | | | | | ______
12 * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
13 * TBG-A-S --| | | | | | |______|
14 * TBG-B-S --|_____| |_______| |_______|
20 #include <linux/clk-provider.h>
201 .parent_names = (const char *[]){ "TBG-A-P", \
202 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
211 .parent_names = (const char *[]){ "TBG-A-P", \
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