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/linux/Documentation/devicetree/bindings/clock/
H A Dmarvell,armada-3700-uart-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Pali Rohár <pali@kernel.org>
13 const: marvell,armada-3700-uart-clock
17 - description: UART Clock Control Register
18 - description: UART 2 Baud Rate Divisor Register
23 "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
26 It is suggest to specify at least one TBG clock to achieve
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H A Darmada3700-tbg-clock.txt6 The TBG clock consumer should specify the desired clock by having the
9 The following is a list of provided IDs and clock names on Armada 3700:
10 0 = TBG A P
11 1 = TBG B P
12 2 = TBG A S
13 3 = TBG B S
16 - compatible : shall be "marvell,armada-3700-tbg-clock"
17 - reg : must be the register address of North Bridge PLL register
18 - #clock-cells : from common clock binding; shall be set to 1
22 tbg: tbg@13200 {
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H A Darmada3700-periph-clock.txt12 The following is a list of provided IDs for Armada 3700 North bridge clocks:
14 -----------------------------------
33 The following is a list of provided IDs for Armada 3700 South bridge clocks:
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
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/linux/drivers/clk/mvebu/
H A Darmada-37xx-tbg.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 #include <linux/clk-provider.h>
47 static const struct tbg_def tbg[NUM_TBG] = { variable
48 {"TBG-A-P", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL8, TBG_A_VCODIV_DIFF},
49 {"TBG-B-P", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL8, TBG_B_VCODIV_DIFF},
50 {"TBG-A-S", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL1, TBG_A_VCODIV_SE},
51 {"TBG-B-S", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL1, TBG_B_VCODIV_SE},
60 return ((val >> ptbg->fbdiv_offset) & TBG_DIV_MASK) << 2; in tbg_get_mult()
70 div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK; in tbg_get_div()
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H A Darmada-37xx-periph.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * TBG-A-P --| | | | | | ______
12 * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
13 * TBG-A-S --| | | | | | |______|
14 * TBG-B-S --|_____| |_______| |_______|
20 #include <linux/clk-provider.h>
201 .parent_names = (const char *[]){ "TBG-A-P", \
202 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
211 .parent_names = (const char *[]){ "TBG-A-P", \
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/linux/arch/arm64/boot/dts/marvell/
H A Darmada-37xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
34 psci-area@4000000 {
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/linux/drivers/ata/
H A Dsata_promise.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sata_promise.c - Promise SATA
7 * Please ALWAYS copy linux-ide@vger.kernel.org
10 * Copyright 2003-2004 Red Hat, Inc.
13 * as Documentation/driver-api/libata.rst
38 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
40 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
46 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
49 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
57 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
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