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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmarvell,armada-3700-uart-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Pali Rohár <pali@kernel.org>
13 const: marvell,armada-3700-uart-clock
17 - description: UART Clock Control Register
18 - description: UART 2 Baud Rate Divisor Register
23 "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
26 It is suggest to specify at least one TBG clock to achieve
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H A Darmada3700-tbg-clock.txt6 The TBG clock consumer should specify the desired clock by having the
9 The following is a list of provided IDs and clock names on Armada 3700:
10 0 = TBG A P
11 1 = TBG B P
12 2 = TBG A S
13 3 = TBG B S
16 - compatible : shall be "marvell,armada-3700-tbg-clock"
17 - reg : must be the register address of North Bridge PLL register
18 - #clock-cells : from common clock binding; shall be set to 1
22 tbg: tbg@13200 {
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H A Darmada3700-periph-clock.txt12 The following is a list of provided IDs for Armada 3700 North bridge clocks:
14 -----------------------------------
33 The following is a list of provided IDs for Armada 3700 South bridge clocks:
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
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/freebsd/sys/arm/mv/clk/
H A Da37x0_tbg.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
71 { -1, 0 }
83 static const struct a37x0_tbg_def tbg[NUM_TBG] = { variable
84 {"TBG-A-P", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL8, TBG_A_VCODIV_DIFF, 9},
85 {"TBG-B-P", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL8,
87 {"TBG-A-S", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL1, TBG_A_VCODIV_SEL, 9},
88 {"TBG-B-S", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL1, TBG_B_VCODIV_SEL, 25}
122 *val = bus_read_4(sc->res, offset); in a37x0_tbg_read_4()
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/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-37xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
34 psci-area@4000000 {
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/freebsd/sys/dev/ioat/
H A Dioat.c1 /*-
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
111 device_printf(ioat->device, __VA_ARGS__); \
121 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled");
125 0, "Set log level (0-3) for ioat(4). Higher is more verbose.");
132 * OS <-> Driver interface structures
166 { 0x34308086, "TBG IOAT Ch0" },
167 { 0x34318086, "TBG IOAT Ch1" },
168 { 0x34328086, "TBG IOAT Ch2" },
169 { 0x34338086, "TBG IOAT Ch3" },
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/freebsd/sys/arm/mv/
H A Da37x0_spi.c1 /*-
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
62 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val))
64 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off))
65 #define A37X0_SPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
66 #define A37X0_SPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
72 * to retrieve the actual TBG and PLL settings.
107 { "marvell,armada-3700-spi", 1 },
134 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in a37x0_spi_probe()
150 sc->sc_dev = dev; in a37x0_spi_attach()
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