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/linux/arch/riscv/lib/
H A Dmemmove.S36 * Reverse Copy: t4 - Index counter of dest
53 add t4, a0, a2
68 andi t6, t4, -SZREG
162 sub a5, a4, t4 /* Find the difference between src and dest */
197 addi t4, t4, (-2 * SZREG)
201 REG_S t2, ( 1 * SZREG)(t4)
203 beq t4, a2, 2f
210 REG_S t2, ( 0 * SZREG)(t4)
212 bne t4, t5, 1b
214 mv t4, t5 /* Fix the dest pointer in case the loop was broken */
[all …]
H A Dstrncmp.S66 * t0, t1, t2, t3, t4, t5, t6
72 add t4, a0, a2
76 andi t6, t4, -SZREG
121 bge a0, t4, 5f
H A Duaccess.S124 fixup REG_L t4, 7*SZREG(a1), 10f
132 fixup REG_S t4, 7*SZREG(a0), 10f
163 * t4 - current shift
167 sub t4, a5, t3
184 sll a2, a5, t4
/linux/arch/alpha/lib/
H A Dev67-strrchr.S36 insbl a1, 1, t4 # U : 000000000000ch00
41 or t2, t4, a1 # E : 000000000000chch
48 sll a1, 48, t4 # U : chch000000000000
50 or t4, a1, a1 # E : chch00000000chch
56 mskqh t5, a0, t4 # E : Complete garbage mask
58 cmpbge zero, t4, t4 # E : bits set iff byte is garbage
61 andnot t1, t4, t1 # E : clear garbage from null test
62 andnot t3, t4, t3 # E : clear garbage from char test
84 negq t1, t4 # E : isolate first null byte match
85 and t1, t4, t4 # E :
[all …]
H A Dstrrchr.S31 lda t4, -1 # .. e1 : build garbage mask
34 mskqh t4, a0, t4 # e0 :
37 cmpbge zero, t4, t4 # .. e1 : bits set iff byte is garbage
39 andnot t1, t4, t1 # .. e1 : clear garbage from null test
40 andnot t3, t4, t3 # e0 : clear garbage from char test
56 negq t1, t4 # e0 : isolate first null byte match
57 and t1, t4, t4 # e1 :
58 subq t4, 1, t5 # e0 : build a mask of the bytes up to...
59 or t4, t5, t4 # e1 : ... and including the null
61 and t3, t4, t3 # e0 : mask out char matches after null
H A Dstrchr.S27 lda t4, -1 # .. e1 : build garbage mask
30 mskqh t4, a0, t4 # e0 :
33 cmpbge zero, t4, t4 # .. e1 : bits set iff byte is garbage
38 andnot t0, t4, t0 # e0 : clear garbage bits
58 and t0, 0xaa, t4 # e0 :
61 cmovne t4, 1, t4 # .. e1 :
63 addq v0, t4, v0 # .. e1 :
H A Dev67-strchr.S40 lda t4, -1 # E : build garbage mask
42 mskqh t4, a0, t4 # U : only want relevant part of first quad
50 cmpbge zero, t4, t4 # E : bits set iff byte is garbage
58 andnot t0, t4, t0 # E : clear garbage bits
/linux/lib/crypto/x86/
H A Dpoly1305-x86_64-cryptogams.pl419 my ($H0,$H1,$H2,$H3,$H4, $T0,$T1,$T2,$T3,$T4, $D0,$D1,$D2,$D3,$D4, $MASK) =
892 vpunpckhqdq $T1,$T0,$T4 # 4
896 vpsrlq \$40,$T4,$T4 # 4
904 vpor 32(%rcx),$T4,$T4 # padbit, yes, always
985 vpmuludq $T4,$D4,$D4 # d4 = h4*r0
988 vpmuludq 0x20(%rsp),$T4,$H0 # h4*s1
1011 vpmuludq $T4,$H4,$H0 # h4*s2
1022 vpmuludq $T4,$H3,$H0 # h4*s3
1034 vpmuludq $T4,$H4,$T4 # h4*s4
1037 vpaddq $T4,$D3,$D3 # d3 += h4*s4
[all …]
/linux/arch/x86/crypto/
H A Dnh-avx2-x86_64.S31 #define T4 %ymm12 macro
49 vpshufd $0x10, T0, T4
57 vpmuludq T4, T0, T0
148 vinserti128 $0x1, T2_XMM, T0, T4 // T4 = (0A 1A 2A 3A)
153 vpaddq T5, T4, T4
155 vpaddq T4, T0, T0
/linux/lib/crypto/riscv/
H A Dpoly1305-riscv.pl26 ($t0,$t1,$t2,$t3,$t4,$t5,$t6)=map("x$_",(5..7,28..31));
128 ($s0,$s1,$s2,$s3,$t3,$t4,$in0,$in1,$t2);
519 lw $t4,16($inp)
531 sllw $t4,$t4,$t5
532 or $d3,$d3,$t4
537 andi $t4,$h4,-4
541 addw $t4,$t4,$t3
543 addw $d0,$d0,$t4 # ... and residue
544 sltu $t4,$d0,$t4
547 addw $h0,$h0,$t4 # carry
[all …]
/linux/arch/arm64/crypto/
H A Dsm4-ce-gcm-core.S53 r4, r5, m4, m5, T4, T5, \ argument
57 ext T4.16b, m5.16b, m5.16b, #8; \
65 pmull T5.1q, m4.1d, T4.1d; \
69 pmull2 T4.1q, m4.2d, T4.2d; \
77 eor T4.16b, T4.16b, T5.16b; \
81 ext T5.16b, RZERO.16b, T4.16b, #8; \
85 ext T4.16b, T4.16b, RZERO.16b, #8; \
93 eor r5.16b, r5.16b, T4.16b; \
136 r4, r5, m4, m5, T4, T5) \ argument
142 ext T4.16b, m5.16b, m5.16b, #8; \
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/linux/lib/crypto/arm/
H A Dsha256-armv4.pl51 $inp="r1"; $t4="r1";
78 str $inp,[sp,#17*4] @ make room for $t4
95 str $inp,[sp,#17*4] @ make room for $t4
127 ldr $t4,[sp,#`($i+15)%16`*4] @ from future BODY_16_xx
144 @ ldr $t4,[sp,#`($i+14)%16`*4]
147 mov $t2,$t4,ror#$sigma1[0]
149 eor $t2,$t2,$t4,ror#$sigma1[1]
152 eor $t2,$t2,$t4,lsr#$sigma1[2] @ sigma1(X[i+14])
153 ldr $t4,[sp,#`($i+9)%16`*4]
159 add $t1,$t1,$t4 @ X[i]
[all …]
/linux/tools/testing/selftests/bpf/prog_tests/
H A Dtracing_struct.c47 ASSERT_EQ(skel->bss->t4_a_a, 10, "t4:a.a"); in test_struct_args()
48 ASSERT_EQ(skel->bss->t4_b, 1, "t4:b"); in test_struct_args()
49 ASSERT_EQ(skel->bss->t4_c, 2, "t4:c"); in test_struct_args()
50 ASSERT_EQ(skel->bss->t4_d, 3, "t4:d"); in test_struct_args()
51 ASSERT_EQ(skel->bss->t4_e_a, 2, "t4:e.a"); in test_struct_args()
52 ASSERT_EQ(skel->bss->t4_e_b, 3, "t4:e.b"); in test_struct_args()
53 ASSERT_EQ(skel->bss->t4_ret, 21, "t4 ret"); in test_struct_args()
/linux/arch/mips/lib/
H A Dcsum_partial.S33 #define t4 $12 macro
182 CSUM_BIGCHUNK1(src, 0x00, sum, t0, t1, t3, t4)
193 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
194 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
195 CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
196 CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4)
208 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
209 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
217 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
476 LOAD(t4, UNIT(4)(src))
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/linux/drivers/net/ethernet/chelsio/
H A DKconfig70 tristate "Chelsio Communications T4/T5/T6 Ethernet support"
77 This driver supports Chelsio T4, T5 & T6 based gigabit, 10Gb Ethernet
93 bool "Data Center Bridging (DCB) Support for Chelsio T4/T5/T6 cards"
115 tristate "Chelsio Communications T4/T5/T6 Virtual Function Ethernet support"
118 This driver supports Chelsio T4, T5 & T6 based gigabit, 10Gb Ethernet
/linux/arch/arm/crypto/
H A Daes-cipher-core.S42 .macro __hround, out0, out1, in0, in1, in2, in3, t3, t4, enc, sz, op, oldcpsr
65 __select \t4, \in0, 3
68 __select \t4, \in2, 3
72 __load \t4, \t4, 3, \sz, \op
87 eor \out1, \out1, \t4, ror #8
H A Daes-neonbs-core.S297 t0, t1, t2, t3, t4, t5, t6, t7, inv
305 vext.8 \t4, \x4, \x4, #12
308 veor \x4, \x4, \t4
325 veor \t4, \t4, \x3
331 veor \t4, \t4, \x7
337 veor \x2, \t0, \t4
346 veor \x3, \t0, \t4
353 t0, t1, t2, t3, t4, t5, t6, t7
358 vld1.8 {\t4-\t5}, [bskey, :256]!
363 veor \x4, \x4, \t4
[all …]
/linux/arch/loongarch/mm/
H A Dpage.S48 ld.d t4, a1, 32
61 st.d t4, a0, 32
63 ld.d t4, a1, 96
76 st.d t4, a0, -32
/linux/arch/riscv/include/asm/
H A Dvector.h207 "add t0, t0, t4\n\t" in __riscv_v_vstate_save()
209 "add t0, t0, t4\n\t" in __riscv_v_vstate_save()
211 "add t0, t0, t4\n\t" in __riscv_v_vstate_save()
213 : : "r" (datap) : "memory", "t0", "t4"); in __riscv_v_vstate_save()
243 "add t0, t0, t4\n\t" in __riscv_v_vstate_restore()
245 "add t0, t0, t4\n\t" in __riscv_v_vstate_restore()
247 "add t0, t0, t4\n\t" in __riscv_v_vstate_restore()
249 : : "r" (datap) : "memory", "t0", "t4"); in __riscv_v_vstate_restore()
275 asm volatile (THEAD_VSETVLI_T4X0E8M8D1 : : : "t4"); in __riscv_v_vstate_discard()
H A Dcompat.h68 compat_ulong_t t4; member
105 cregs->t4 = (compat_ulong_t) regs->t4; in regs_to_cregs()
142 regs->t4 = (unsigned long) cregs->t4; in cregs_to_regs()
/linux/lib/zlib_dfltcc/
H A Ddfltcc_util.h42 const Byte *t4 = op2 ? *op2 : NULL; in dfltcc() local
48 register const Byte *r4 __asm__("r4") = t4; in dfltcc()
64 t2 = r2; t3 = r3; t4 = r4; t5 = r5; in dfltcc()
95 *op2 = t4; in dfltcc()
/linux/arch/loongarch/include/asm/vdso/
H A Dgettimeofday.h30 : "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", in gettimeofday_fallback()
49 : "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", in clock_gettime_fallback()
68 : "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", in clock_getres_fallback()
/linux/arch/sparc/lib/
H A Dchecksum_32.S20 #define CSUM_BIGCHUNK(buf, offset, sum, t0, t1, t2, t3, t4, t5) \ argument
25 ldd [buf + offset + 0x10], t4; \
29 addxcc t4, sum, sum; \
164 #define CSUMCOPY_BIGCHUNK_ALIGNED(src, dst, sum, off, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
168 EX(ldd [src + off + 0x10], t4); \
175 addxcc t4, sum, sum; \
176 EX(std t4, [dst + off + 0x10]); \
186 #define CSUMCOPY_BIGCHUNK(src, dst, sum, off, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
189 EX(ldd [src + off + 0x10], t4); \
199 EX(st t4, [dst + off + 0x10]); \
[all …]
/linux/arch/x86/include/asm/
H A Dsyscall_wrapper.h63 #define SYSCALL_PT_ARG6(m, t1, t2, t3, t4, t5, t6) \ argument
64 SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5), m(t6, (regs->bp))
65 #define SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5) \ argument
66 SYSCALL_PT_ARG4(m, t1, t2, t3, t4), m(t5, (regs->di))
67 #define SYSCALL_PT_ARG4(m, t1, t2, t3, t4) \ argument
68 SYSCALL_PT_ARG3(m, t1, t2, t3), m(t4, (regs->si))
/linux/arch/sparc/include/asm/
H A Dbackoff.h24 * On all cpus prior to SPARC-T4 we do three dummy reads of the
28 * For SPARC-T4 and later we have a special "pause" instruction
31 * unless a disrupting trap happens first. SPARC-T4 specifically

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