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Searched full:svade (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml265 - const: svade
267 The standard Svade supervisor-level extension for SW-managed PTE A/D
271 Both Svade and Svadu extensions control the hardware behavior when
274 1) Neither Svade nor Svadu present in DT => It is technically
275 unknown whether the platform uses Svade or Svadu. Supervisor
278 2) Only Svade present in DT => Supervisor must assume Svade to be
282 4) Both Svade and Svadu present in DT => Supervisor must assume
290 privileged ISA specification. Please refer to Svade dt-binding
/linux/arch/riscv/kernel/
H A Dcpufeature.c293 /* SVADE has already been detected, use SVADE only */ in riscv_ext_svadu_validate()
586 __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
/linux/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c522 KVM_ISA_EXT_ARR(SVADE), in isa_ext_single_id_to_str()
1166 KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE);
/linux/arch/riscv/kvm/
H A Dvcpu_onereg.c45 KVM_ISA_EXT_ARR(SVADE),
253 * Svade can't be disabled unless we support Svadu. in kvm_riscv_vcpu_isa_disable_allowed()
H A Dvcpu.c561 !riscv_isa_extension_available(isa, SVADE)) in kvm_riscv_vcpu_setup_config()
/linux/arch/riscv/include/asm/
H A Dpgtable.h750 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By