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/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml174 - const: svade
176 The standard Svade supervisor-level extension for SW-managed PTE A/D
180 Both Svade and Svadu extensions control the hardware behavior when
183 1) Neither Svade nor Svadu present in DT => It is technically
184 unknown whether the platform uses Svade or Svadu. Supervisor
187 2) Only Svade present in DT => Supervisor must assume Svade to be
191 4) Both Svade and Svadu present in DT => Supervisor must assume
199 privileged ISA specification. Please refer to Svade dt-binding
/linux/arch/riscv/kernel/
H A Dcpufeature.c270 /* SVADE has already been detected, use SVADE only */ in riscv_ext_svadu_validate()
538 __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
/linux/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c519 KVM_ISA_EXT_ARR(SVADE), in isa_ext_single_id_to_str()
1160 KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE);
/linux/arch/riscv/kvm/
H A Dvcpu.c561 !riscv_isa_extension_available(isa, SVADE)) in kvm_riscv_vcpu_setup_config()
/linux/arch/riscv/include/asm/
H A Dpgtable.h730 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By