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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
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/linux/Documentation/arch/x86/x86_64/
H A Dfred.rst1 .. SPDX-License-Identifier: GPL-2.0
11 privilege level (ring transitions). The FRED architecture was
20 establishes the full supervisor context and that event return
33 The LKGS instruction can be used by 64-bit operating systems that do
46 framework must be implemented to facilitate the event-to-handler
48 once an event is delivered, and employs a two-level dispatch.
50 The first level dispatching is event type based, and the second level
53 Full supervisor/user context
56 FRED event delivery atomically save and restore full supervisor/user
86 event handling, and each stack level should be configured to use a
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/linux/arch/microblaze/include/asm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
27 unsigned long w:1; /* Write-thru cache mode */
36 # define PP_RWXX 0 /* Supervisor read/write, User none */
37 # define PP_RWRX 1 /* Supervisor read/write, User read */
38 # define PP_RWRW 2 /* Supervisor read/write, User read/write */
39 # define PP_RXRX 3 /* Supervisor read, User read */
44 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
46 unsigned long n:1; /* No-execute */
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H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 * low level task data that entry.S needs immediate access to
22 * - this struct should fit entirely inside of one cache line
23 * - this struct shares the supervisor stack pages
24 * - if the contents of this structure are changed, the assembly constants
38 /* non-volatile registers */
61 unsigned long flags; /* low level flags */
62 unsigned long status; /* thread-synchronous flags */
85 return (struct thread_info *)(sp & ~(THREAD_SIZE-1)); in current_thread_info()
93 * - these are process state flags that various assembly files may
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/linux/Documentation/arch/riscv/
H A Duabi.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Linux User ABI
7 ------------------------------------
10 Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA
16 #. Single-letter extensions come first, in canonical order.
19 #. All multi-letter extensions will be separated from other extensions by an
23 single-letter extensions and before any higher-privileged extensions.
31 #. Standard supervisor-level extensions (starting with 'S') will be listed
32 after standard unprivileged extensions. If multiple supervisor-level
35 #. Standard machine-level extensions (starting with 'Zxm') will be listed
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/linux/arch/x86/kvm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
65 return ((2ULL << (e - s)) - 1) << s; in kvm_mmu_max_gfn()
83 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1;
88 return mmu->root_role.cr4_smep;
132 if (likely(vcpu->arch.mmu->roo in kvm_get_pcid()
265 gfn_to_index(gfn_t gfn,gfn_t base_gfn,int level) gfn_to_index() argument
274 __kvm_mmu_slot_lpages(struct kvm_memory_slot * slot,unsigned long npages,int level) __kvm_mmu_slot_lpages() argument
281 kvm_mmu_slot_lpages(struct kvm_memory_slot * slot,int level) kvm_mmu_slot_lpages() argument
286 kvm_update_page_stats(struct kvm * kvm,int level,int count) kvm_update_page_stats() argument
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/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
239 #define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
240 #define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
248 #define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
249 #define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
258 #define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
35 * low level task data that entry.S needs immediate access to
36 * - this struct should fit entirely inside of one cache line
37 * - this struct shares the supervisor stack pages
38 * - if the contents of this structure are changed, the assembly constants
45 unsigned long flags; /* low level flags */
75 #define get_thread_info(ti) get_task_struct((ti)->task)
76 #define put_thread_info(ti) put_task_struct((ti)->task)
84 * - pending work-to-be-done flags are in LSW
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/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-8xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * We also use the two level tables, but we can put the real bits in them
10 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
16 * the TLB entry (24 and 25) for these indicators. Although the level 1
18 * set these at the page level since they get copied from the Mx_TWC
21 * These will get masked from the level 2 descriptor at TLB load time, and
46 #define _PAGE_NA 0x0200 /* Supervisor NA, User no access */
47 #define _PAGE_RO 0x0600 /* Supervisor RO, User no access */
84 #include <asm/pgtable-masks.h>
138 pte_update(vma->vm_mm, address, ptep, clr, set, huge); in __ptep_set_access_flags()
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/linux/arch/mips/include/asm/octeon/
H A Docteon.h6 * Copyright (C) 2004-2008 Cavium Networks
57 /* Start of block referenced by assembly code - do not change! */
66 /* End of This block referenced by assembly code - do not change! */
117 /* End of This block referenced by assembly code - do not change! */
124 * Warning low bit scrambled in little-endian.
182 /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
189 /* OCTEON II - Selects the bit in the counter used for
196 /* OCTEON II - This field is an extension of
199 /* R/W If set, marked write-buffer entries time out
201 * write-buffer entries use the maximum timeout. */
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/linux/arch/nios2/include/asm/
H A Dthread_info.h2 * NiosII low-level thread information
30 * low level task data that entry.S needs immediate access to
31 * - this struct should fit entirely inside of one cache line
32 * - this struct shares the supervisor stack pages
33 * - if the contents of this structure are changed, the assembly constants
38 unsigned long flags; /* low level flags */
62 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); in current_thread_info()
68 * - these are process state flags that various assembly files may need to
70 * - pending work-to-be-done flags are in LSW
71 * - other flags in MSW
/linux/arch/loongarch/include/asm/
H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * thread_info.h: LoongArch low-level thread information
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
18 * low level task data that entry.S needs immediate access to
19 * - this struct should fit entirely inside of one cache line
20 * - this struct shares the supervisor stac
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/linux/arch/arm/mach-imx/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0
42 * Set all MPROTx to be non-bufferable, trusted for R/W, in imx_set_aips()
43 * not forced to user-mode. in imx_set_aips()
49 * Set all OPACRx to be non-bufferable, to not require in imx_set_aips()
50 * supervisor privilege level for access, allow for in imx_set_aips()
/linux/arch/arc/include/asm/
H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 * anyways one page allocation, thus slab alloc can be short-circuited and
32 * low level task data that entry.S needs immediate access to
33 * - this struct should fit entirely inside of one cache line
34 * - this struct shares the supervisor stack pages
35 * - if the contents of this structure are changed, the assembly constants
39 unsigned long flags; /* low level flags */
49 * - this is not related to init_task per se
62 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); in current_thread_info()
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/linux/arch/nios2/mm/
H A Dfault.c7 * Copyright (C) 1995-2000 Ralf Baechle
32 #define EXC_SUPERV_INSN_ACCESS 9 /* Supervisor only instruction address */
33 #define EXC_SUPERV_DATA_ACCESS 11 /* Supervisor only data address */
48 struct mm_struct *mm = tsk->mm; in do_page_fault()
56 regs->ea -= 4; in do_page_fault()
59 * We fault-in kernel-space virtual memory on-demand. The in do_page_fault()
105 if (!(vma->vm_flags & VM_EXEC)) in do_page_fault()
109 if (!(vma->vm_flags & VM_READ)) in do_page_fault()
113 if (!(vma->vm_flags & VM_WRITE)) in do_page_fault()
173 "cause %ld\n", current->comm, SIGSEGV, address, cause); in do_page_fault()
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/linux/arch/x86/kvm/mmu/
H A Dpaging_tmpl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
19 * The MMU needs to be able to access/walk 32-bit and 64-bit guest page tables,
21 * once per guest PTE type. The per-type defines are #undef'd at the end.
50 (((1ULL << PT32_DIR_PSE36_SIZE) -
81 int level; global() member
202 unsigned level, index; FNAME() local
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/linux/arch/xtensa/include/asm/
H A Dthread_info.h2 * include/asm-xtensa/thread_info.h
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
24 * low level task data that entry.S needs immediate access to
25 * - this struct should fit entirely inside of one cache line
26 * - this struct shares the supervisor stack pages
27 * - if the contents of this structure are changed, the assembly constants
50 unsigned long flags; /* low level flags */
51 unsigned long status; /* thread-synchronous flags */
65 * If i-th bit is set then coprocessor state is loaded into the
113 * - these are process state flags that various assembly files may need to access
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/linux/Documentation/core-api/
H A Derrseq.rst13 It's implemented as an unsigned 32-bit value. The low order bits are
28 +--------------------------------------+----+------------------------+
30 +--------------------------------------+----+------------------------+
32 +--------------------------------------+----+------------------------+
54 They're all handing him work to do -- so much he can't keep track of who
60 but he can't keep track of things at that level of detail, all he can
78 struct supervisor {
83 struct supervisor su;
103 errseq_set(&wd.wd_err, -EIO);
115 to do a one-off job for him. He's not really watching the worker
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/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v3.1
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 -
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/linux/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #include <asm/asm-const.h>
46 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
114 #define PP_RWXX 0 /* Supervisor read/write, User none */
115 #define PP_RWRX 1 /* Supervisor read/write, User read */
116 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
117 #define PP_RXRX 3 /* Supervisor read, User read */
118 #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
192 return -1; in shift_to_mmu_psize()
211 return -1; in ap_to_shift()
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/linux/arch/mips/include/asm/
H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* thread_info.h: MIPS low-level thread information
5 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
19 * low level task data that entry.S needs immediate access to
20 * - this struct should fit entirely inside of one cache line
21 * - this struct shares the supervisor stack pages
22 * - if the contents of this structure are changed, the assembly constants
27 unsigned long flags; /* low level flags */
99 #define THREAD_MASK (THREAD_SIZE - 1UL)
105 * - these are process state flags that various assembly files may need to
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/linux/Documentation/userspace-api/
H A Dseccomp_filter.rst25 to time-of-check-time-of-use (TOCTOU) attacks that are common in system
65 call will return -1 and set errno to ``EINVAL``.
73 true, ``-EACCES`` will be returned. This requirement ensures that filter
82 The above call returns 0 on success and non-zero on error.
106 task without executing the system call. ``siginfo->si_call_addr``
108 ``siginfo->si_syscall`` and ``siginfo->si_arch`` will indicate which
111 instruction). The return value register will contain an arch-
112 dependent value -- if resuming execution, set it to something
114 it with ``-ENOSYS`` could overwrite some useful information.)
122 Results in the lower 16-bits of the return value being passed
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/linux/arch/x86/include/asm/fpu/
H A Dtypes.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 /* 8*10 bytes for each FP-reg = 80 bytes: */
56 /* 8*16 bytes for each FP-reg = 128 bytes: */
59 /* 16*16 bytes for each XMM-reg = 256 bytes: */
89 /* 8*10 bytes for each FP-reg = 80 bytes: */
181 * There are 16x 256-bit AVX registers named YMM0-YMM15.
182 * The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15)
199 * State component 3 is used for the 4 128-bit bounds registers
206 * State component 4 is used for the 64-bit user-mode MPX
207 * configuration register BNDCFGU and the 64-bit MPX status
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/linux/arch/m68k/coldfire/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0-or-later
3 * entry.S -- interrupt and exception processing for ColdFire
5 * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
9 * Copyright (C) 2004-2006 Macq Electronique SA. (www.macqel.com)
31 #include <asm/asm-offsets.h>
36 * Define software copies of the supervisor and user stack pointers.
71 andl #-THREAD_SIZE,%d2 /* at start of kernel stack */
75 btst #(TIF_SYSCALL_TRACE%8),%a0@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
83 movel #-ENOSYS,%d2 /* strace needs -ENOSYS in PT_OFF_D0 */
108 andl #-THREAD_SIZE,%d1 /* at base of kernel stack */
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/linux/drivers/iommu/intel/
H A Dpasid.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * pasid.h - PASID idr, table and entry header
22 #define is_pasid_enabled(entry) (((entry)->lo >> 3) & 0x1)
23 #define get_pasid_dir_size(entry) (1 << ((((entry)->lo >> 9) & 0x7) + 7))
30 * The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
31 * level translation, otherwise, 4-level paging will be used.
57 return READ_ONCE(pde->val) & PASID_PTE_PRESENT; in pasid_pde_is_present()
67 return phys_to_virt(READ_ONCE(pde->val) & PDE_PFN_MASK); in get_pasid_table_from_pde()
73 return READ_ONCE(pte->val[0]) & PASID_PTE_PRESENT; in pasid_pte_is_present()
79 return READ_ONCE(pte->val[0]) & PASID_PTE_FPD; in pasid_pte_is_fault_disabled()
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