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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,usb-ss.yaml7 title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
13 Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
30 - description: SuperSpeed pipe clock
/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml190 When set, all SuperSpeed bus instances in park mode are disabled.
274 flow-controlled endpoint. It is only used for SuperSpeed.
275 The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
291 The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
303 for SuperSpeed operation.
304 Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
317 Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
H A Dnvidia,tegra124-xusb.yaml50 - description: XUSB SuperSpeed clock
51 - description: XUSB SuperSpeed clock divider
52 - description: XUSB SuperSpeed source clock
76 - description: reset for the SuperSpeed logic
H A Dmicrochip,usb5744.yaml10 Microchip's USB5744 SmartHubTM IC is a 4 port, SuperSpeed (SS)/Hi-Speed (HS),
14 speeds. The new SuperSpeed hubs operate in parallel with the USB 2.0
15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
H A Dnvidia,tegra186-xusb.yaml39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
97 - description: XUSBA power domain (for SuperSpeed)
H A Dnvidia,tegra194-xusb.yaml39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
98 - description: XUSBA power domain (for SuperSpeed)
H A Dnvidia,tegra234-xusb.yaml69 - description: XUSB SuperSpeed clock
70 - description: XUSB SuperSpeed source clock
128 - description: XUSBA power domain (for SuperSpeed)
H A Dnvidia,tegra-xudc.yaml11 USB 3.0 SuperSpeed protocols.
79 - description: XUSBA(superspeed) power-domain
H A Dusb-switch.yaml25 description: Possible handler of SuperSpeed signals retiming
H A Ddwc3-cavium.txt1 Cavium SuperSpeed DWC3 USB SoC controller
H A Dfsl,ls1028a.yaml7 title: Freescale layerscape SuperSpeed DWC3 USB SoC controller
H A Dti,hd3ss3220.yaml13 HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel
H A Drockchip,rk3399-dwc3.yaml7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
H A Drockchip,dwc3.yaml7 title: Rockchip SuperSpeed DWC3 USB SoC controller
/linux/Documentation/driver-api/usb/
H A Dusb3-debug-port.rst75 [ 1815.983374] usb 4-3: new SuperSpeed USB device number 4 using xhci_hcd
143 [ 79.454780] usb 2-2.1: new SuperSpeed USB device number 3 using xhci_hcd
H A Dpower-management.rst655 another hub. The expectation is that all superspeed ports have a
662 peer ports are simply the hi-speed and superspeed interface pins that
666 While a superspeed port is powered off a device may downgrade its
671 before their superspeed peer is permitted to power-off. The implication is
672 that the setting ``pm_qos_no_power_off`` to zero on a superspeed port may
675 if it wants to guarantee that a superspeed port will power-off.
677 2. Port resume is sequenced to force a superspeed port to power-on prior to its
H A Ddwc3.rst2 Synopsys DesignWare Core SuperSpeed USB 3.0 Controller
11 The *Synopsys DesignWare Core SuperSpeed USB 3.0 Controller*
12 (hereinafter referred to as *DWC3*) is a USB SuperSpeed compliant
41 your IP team and/or *Synopsys DesignWare Core SuperSpeed USB 3.0
53 7. SuperSpeed Bulk Streams
89 to a value that's divisible by *wMaxPacketSize* (1024 on SuperSpeed,
/linux/include/linux/usb/
H A Dgadget.h222 * @comp_desc: In case of SuperSpeed support, this is the endpoint companion
374 * @ssp_rate: Current connected SuperSpeed Plus signaling rate and lane count.
375 * @max_ssp_rate: Maximum SuperSpeed Plus signaling rate and lane count the UDC
452 /* USB SuperSpeed Plus only */
603 * gadget_is_superspeed() - return true if the hardware handles superspeed
604 * @g: controller that might support superspeed
613 * superspeed plus
614 * @g: controller that might support superspeed plus
H A Dch9.h35 /* USB 3.2 SuperSpeed Plus phy signaling rate generation and lane count */
/linux/drivers/usb/core/
H A Dquirks.c385 /* Avermedia Live Gamer Ultra 2.1 (GC553G2) - BOS descriptor fetch hangs at SuperSpeed Plus */
449 /* ASUS TUF 4K PRO - BOS descriptor fetch hangs at SuperSpeed Plus */
465 /* Elgato 4K X - BOS descriptor fetch hangs at SuperSpeed Plus */
582 /* UGREEN 35871 - BOS descriptor fetch hangs at SuperSpeed Plus */
595 /* ezcap401 - BOS descriptor fetch hangs at SuperSpeed Plus */
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-s922x-khadas-vim3.dts20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
H A Dmeson-g12b-a311d-khadas-vim3.dts20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
/linux/drivers/usb/mtu3/
H A DKconfig13 Dual Role SuperSpeed USB controller. You can select usb
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-typec-displayport47 USB SuperSpeed protocol. From user perspective pin assignments C
/linux/drivers/usb/gadget/
H A Dcomposite.c350 if (!config->superspeed && function->ss_descriptors) in usb_add_function()
351 config->superspeed = true; in usb_add_function()
493 * Applicable to devices operating at enhanced superspeed when usb
658 if (!c->superspeed) in config_desc()
702 if (!c->superspeed) in count_configs()
723 * descriptor should be supported by a SuperSpeed device.
762 * A SuperSpeed device shall include the USB2.0 extension descriptor in bos_desc()
777 * The Superspeed USB Capability descriptor shall be implemented by all in bos_desc()
778 * SuperSpeed devices. in bos_desc()
1149 config->superspeed ? " super" : "", in usb_add_config()

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