| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,usb-ss.yaml | 7 title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
13 Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
30 - description: SuperSpeed pipe clock
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | snps,dwc3-common.yaml | 190 When set, all SuperSpeed bus instances in park mode are disabled.
274 flow-controlled endpoint. It is only used for SuperSpeed.
275 The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
291 The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
303 for SuperSpeed operation.
304 Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
317 Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
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| H A D | nvidia,tegra124-xusb.yaml | 50 - description: XUSB SuperSpeed clock
51 - description: XUSB SuperSpeed clock divider
52 - description: XUSB SuperSpeed source clock
76 - description: reset for the SuperSpeed logic
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| H A D | microchip,usb5744.yaml | 10 Microchip's USB5744 SmartHubTM IC is a 4 port, SuperSpeed (SS)/Hi-Speed (HS),
14 speeds. The new SuperSpeed hubs operate in parallel with the USB 2.0
15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
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| H A D | nvidia,tegra234-xusb.yaml | 43 - description: XUSB SuperSpeed clock
44 - description: XUSB SuperSpeed source clock
102 - description: XUSBA power domain (for SuperSpeed)
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| H A D | nvidia,tegra186-xusb.yaml | 39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
97 - description: XUSBA power domain (for SuperSpeed)
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| H A D | nvidia,tegra194-xusb.yaml | 39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
98 - description: XUSBA power domain (for SuperSpeed)
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| H A D | nvidia,tegra-xudc.yaml | 11 USB 3.0 SuperSpeed protocols.
79 - description: XUSBA(superspeed) power-domain
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| H A D | dwc3-cavium.txt | 1 Cavium SuperSpeed DWC3 USB SoC controller
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| H A D | fsl,ls1028a.yaml | 7 title: Freescale layerscape SuperSpeed DWC3 USB SoC controller
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| H A D | usb-switch.yaml | 25 description: Possible handler of SuperSpeed signals retiming
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| H A D | rockchip,rk3399-dwc3.yaml | 7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
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| /linux/Documentation/driver-api/usb/ |
| H A D | usb3-debug-port.rst | 75 [ 1815.983374] usb 4-3: new SuperSpeed USB device number 4 using xhci_hcd
143 [ 79.454780] usb 2-2.1: new SuperSpeed USB device number 3 using xhci_hcd
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| H A D | power-management.rst | 655 another hub. The expectation is that all superspeed ports have a
662 peer ports are simply the hi-speed and superspeed interface pins that
666 While a superspeed port is powered off a device may downgrade its
671 before their superspeed peer is permitted to power-off. The implication is
672 that the setting ``pm_qos_no_power_off`` to zero on a superspeed port may
675 if it wants to guarantee that a superspeed port will power-off.
677 2. Port resume is sequenced to force a superspeed port to power-on prior to its
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| H A D | dwc3.rst | 2 Synopsys DesignWare Core SuperSpeed USB 3.0 Controller
11 The *Synopsys DesignWare Core SuperSpeed USB 3.0 Controller*
12 (hereinafter referred to as *DWC3*) is a USB SuperSpeed compliant
41 your IP team and/or *Synopsys DesignWare Core SuperSpeed USB 3.0
53 7. SuperSpeed Bulk Streams
89 to a value that's divisible by *wMaxPacketSize* (1024 on SuperSpeed,
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| /linux/drivers/usb/core/ |
| H A D | port.c | 523 * may miss a suspend event for the SuperSpeed port. in link_peers()
540 * The SuperSpeed reference is dropped when the HiSpeed port in in link_peers()
542 * SuperSpeed connection to drop since there is no risk of a in link_peers()
578 * usb_port_runtime_resume() event which takes a SuperSpeed ref in unlink_peers()
596 /* Drop the SuperSpeed ref held on behalf of the active HiSpeed port */ in unlink_peers()
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| /linux/include/linux/usb/ |
| H A D | gadget.h | 222 * @comp_desc: In case of SuperSpeed support, this is the endpoint companion
374 * @ssp_rate: Current connected SuperSpeed Plus signaling rate and lane count.
375 * @max_ssp_rate: Maximum SuperSpeed Plus signaling rate and lane count the UDC
449 /* USB SuperSpeed Plus only */
598 * gadget_is_superspeed() - return true if the hardware handles superspeed in gadget_is_otg()
599 * @g: controller that might support superspeed in gadget_is_otg()
608 * superspeed plus
609 * @g: controller that might support superspeed plus
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| H A D | ch9.h | 35 /* USB 3.2 SuperSpeed Plus phy signaling rate generation and lane count */
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| /linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-g12b-s922x-khadas-vim3.dts | 20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
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| H A D | meson-g12b-a311d-khadas-vim3.dts | 20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
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| H A D | meson-sm1-khadas-vim3l.dts | 82 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
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| /linux/drivers/usb/mtu3/ |
| H A D | Kconfig | 13 Dual Role SuperSpeed USB controller. You can select usb
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8-apalis-eval.dtsi | 144 /* Apalis USBH4 SuperSpeed */
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| /linux/drivers/phy/broadcom/ |
| H A D | Kconfig | 31 driver. It supports all versions of Superspeed and
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-typec-displayport | 47 USB SuperSpeed protocol. From user perspective pin assignments C
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