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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dnvidia,tegra210-xusb.yaml42 - description: XUSB SuperSpeed clock
43 - description: XUSB SuperSpeed clock divider
44 - description: XUSB SuperSpeed source clock
68 - description: reset for the SuperSpeed logic
104 - description: XUSBA power domain (for SuperSpeed)
H A Dnvidia,tegra124-xusb.yaml50 - description: XUSB SuperSpeed clock
51 - description: XUSB SuperSpeed clock divider
52 - description: XUSB SuperSpeed source clock
76 - description: reset for the SuperSpeed logic
H A Dmicrochip,usb5744.yaml10 Microchip's USB5744 SmartHubTM IC is a 4 port, SuperSpeed (SS)/Hi-Speed (HS),
14 speeds. The new SuperSpeed hubs operate in parallel with the USB 2.0
15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
H A Dsnps,dwc3.yaml237 When set, all SuperSpeed bus instances in park mode are disabled.
321 flow-controlled endpoint. It is only used for SuperSpeed.
322 The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
338 The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
350 for SuperSpeed operation.
351 Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
364 Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
H A Dnvidia,tegra234-xusb.yaml43 - description: XUSB SuperSpeed clock
44 - description: XUSB SuperSpeed source clock
102 - description: XUSBA power domain (for SuperSpeed)
H A Dnvidia,tegra186-xusb.yaml39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
97 - description: XUSBA power domain (for SuperSpeed)
H A Dnvidia,tegra194-xusb.yaml39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
98 - description: XUSBA power domain (for SuperSpeed)
H A Dnvidia,tegra-xudc.yaml11 USB 3.0 SuperSpeed protocols.
79 - description: XUSBA(superspeed) power-domain
H A Ddwc3-cavium.txt1 Cavium SuperSpeed DWC3 USB SoC controller
H A Dfsl,ls1028a.yaml7 title: Freescale layerscape SuperSpeed DWC3 USB SoC controller
H A Dusb-switch.yaml25 description: Possible handler of SuperSpeed signals retiming
H A Ddwc3-xilinx.txt1 Xilinx SuperSpeed DWC3 USB SoC controller
H A Drockchip,dwc3.txt1 Rockchip SuperSpeed DWC3 USB SoC controller
H A Dti,hd3ss3220.yaml13 HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel
H A Drockchip,dwc3.yaml7 title: Rockchip SuperSpeed DWC3 USB SoC controller
H A Drockchip,rk3399-dwc3.yaml7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
H A Ddwc3-xilinx.yaml7 title: Xilinx SuperSpeed DWC3 USB SoC controller
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,gcc-sc8280xp.yaml32 - description: Primary USB SuperSpeed pipe clock
40 - description: Secondary USB SuperSpeed pipe clock
48 - description: Multiport USB first SuperSpeed pipe clock
49 - description: Multiport USB second SuperSpeed pipe clock
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,usb-ss.yaml7 title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
13 Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
30 - description: SuperSpeed pipe clock
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-g12b-a311d-khadas-vim3.dts20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
H A Dmeson-g12b-s922x-khadas-vim3.dts20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
H A Dmeson-sm1-khadas-vim3l.dts88 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-apalis-eval.dtsi122 /* TODO: Apalis USBH4 SuperSpeed */
/freebsd/lib/libusb/
H A Dlibusb.3520 This function parses the SuperSpeed device capability descriptor from the descriptor given by
525 On success the parsed SuperSpeed device capability descriptor must be freed using the
530 This function is NULL safe and frees a parsed SuperSpeed device capability descriptor given by
/freebsd/share/man/man4/
H A Dudbp.4134 for a USB 3.0 SuperSpeed cable, latency is comparable to 100BaseTX Ethernet

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