Searched full:sonics (Results 1 – 9 of 9) sorted by relevance
60 * Sonics configuration registers are mapped to each core's enumeration65 * [0x0e00-0x0eff] SIBA_R1 registers (sonics >= 2.3)70 #define SIBA_CFG1_OFFSET 0xe00 /**< second configuration block (sonics >= 2.3) */85 #define SIBA_CFG0_TMERRLOGA 0x48 /**< sonics >= 2.3 */86 #define SIBA_CFG0_TMERRLOG 0x50 /**< sonics >= 2.3 */107 /* SIBA_CFG1 registers (sonics >= 2.3) */108 #define SIBA_CFG1_IMERRLOGA 0xa8 /**< (sonics >= 2.3) */109 #define SIBA_CFG1_IMERRLOG 0xb0 /**< sbtmerrlog (sonics >= 2.3) */110 #define SIBA_CFG1_TMPORTCONNID0 0xd8 /**< sonics >= 2.3 */111 #define SIBA_CFG1_TMPORTLOCK0 0xf8 /**< sonics >= 2.3 */[all …]
122 /* Sonics configuration register blocks */123 #define SIBA_CFG_NUM_2_2 1 /**< sonics <= 2.2 maps SIBA_CFG0. */124 #define SIBA_CFG_NUM_2_3 2 /**< sonics <= 2.3 maps SIBA_CFG0 and SIBA_CFG1 */133 /* Sonics/OCP address space mappings */137 #define SIBA_MAX_ADDRSPACE 4 /**< Maximum number of Sonics/OCP183 uint8_t sonics_rev; /**< sonics backplane revision code */188 uint8_t num_cfg_blocks; /**< number of Sonics configuration register
43 * Broadcom Sonics Silicon backplane types and data structures.
270 /* Determine the number of sonics config register blocks */ in siba_eio_read_core_id()
136 * reserve the Sonics configuration register blocks for the in siba_init_dinfo()
50 #define BHND_PCI_SBTOPCI_MBOX 0x028 /**< Sonics to PCI mailbox */51 #define BHND_PCI_BCAST_ADDR 0x050 /**< Sonics broadcast address (pci) */52 #define BHND_PCI_BCAST_DATA 0x054 /**< Sonics broadcast data (pci) */57 #define BHND_PCI_SBTOPCI0 0x100 /**< Sonics to PCI translation 0 */58 #define BHND_PCI_SBTOPCI1 0x104 /**< Sonics to PCI translation 1 */59 #define BHND_PCI_SBTOPCI2 0x108 /**< Sonics to PCI translation 2 */111 /* Sonics to PCI translation types */147 #define BHND_PCIE_SBTOPCI_MBOX BHND_PCI_SBTOPCI_MBOX /**< Sonics to PCI mailbox */148 #define BHND_PCIE_SBTOPCI0 BHND_PCI_SBTOPCI0 /**< Sonics to PCI translation 0 */149 #define BHND_PCIE_SBTOPCI1 BHND_PCI_SBTOPCI1 /**< Sonics to PCI translation 1 */[all …]
5 interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
15 using Arteris NoC, and L4 interconnect using Sonics s3220. This module
699 backplane architecture, based on Sonics Silicon's interconnect IP.700 Each core on the Sonics backplane vends a 4 KiB register block, containing both