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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-sifive.yaml4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
21 - sifive,fu540-c000-spi
22 - sifive,fu740-c000-spi
23 - const: sifive,spi0
26 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
28 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dpwm-sifive.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
30 - sifive,fu540-c000-pwm
31 - sifive,fu740-c000-pwm
32 - const: sifive,pwm0
34 Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
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H A Dpwm-sifive.txt1 SiFive PWM controller
3 Unlike most other PWM controllers, the SiFive PWM controller currently only
10 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
13 - compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
14 Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
15 PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
16 SiFive PWM v0 IP block with no chip integration tweaks.
17 Please refer to sifive-blocks-ip-versioning.txt for details.
27 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dsifive,fu540-c000-pdma.yaml4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 - sifive,fu540-c000-pdma
34 - const: sifive,pdma0
36 Should be "sifive,<chi
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/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A Dfu540-c000.dtsi2 /* Copyright (c) 2018-2019 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
11 compatible = "sifive,fu540-c000", "sifive,fu540";
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
71 compatible = "sifive,u54-mc", "sifive,rocket
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H A Dfu740-c000.dtsi2 /* Copyright (c) 2020 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
11 compatible = "sifive,fu740-c000", "sifive,fu740";
26 compatible = "sifive,bullet0", "riscv";
45 compatible = "sifive,bullet0", "riscv";
72 compatible = "sifive,bullet0", "riscv";
99 compatible = "sifive,bullet0", "riscv";
126 compatible = "sifive,bullet0", "riscv";
185 compatible = "sifive,fu54
[all...]
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dsifive-serial.yaml4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
24 - const: sifive,uart0
27 Should be something similar to "sifive,<chip>-uart"
29 and "sifive,uart<version>" for the general UART IP
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sifive/
H A Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
30 "sifive,fu540-c000-uart". This way, if SoC-specific
33 IP block-specific compatible string (such as "sifive,uart0") should
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/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dsifive,ccache0.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
8 title: SiFive Composable Cache Controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 The SiFive Composable Cache Controller is used to provide access to fast copies
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
36 - sifive,ccache0
37 - sifive,fu540-c000-ccache
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H A Dsifive.yaml4 $id: http://devicetree.org/schemas/riscv/sifive.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
23 - sifive,hifive-unleashed-a00
24 - const: sifive,fu540-c000
25 - const: sifive,fu540
29 - sifive,hifive-unmatched-a00
30 - const: sifive,fu740-c000
[all …]
H A Dcpus.yaml10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
38 - sifive,bullet0
39 - sifive,e5
40 - sifive,e7
41 - sifive,e71
42 - sifive,rocket0
43 - sifive,s7
44 - sifive,u5
45 - sifive,u54
[all …]
H A Dsifive-l2-cache.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 The SiFive Level 2 Cache Controller is used to provide access to fast copies
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
36 - sifive,fu540-c000-ccache
37 - sifive,fu740-c000-ccache
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/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dsifive,ccache0.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
8 title: SiFive Composable Cache Controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 The SiFive Composable Cache Controller is used to provide access to fast copies
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
36 - sifive,ccache0
37 - sifive,fu54
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/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dsifive,clint.yaml4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
7 title: SiFive Core Local Interruptor
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
25 compatible with SiFive ones.
33 - sifive,fu540-c000-clint # SiFive FU540
37 - const: sifive,clint0 # SiFive CLINT v0 IP block
47 - const: sifive,clint0
53 Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
54 when compatible with a SiFive CLINT. Please refer to
55 sifive-blocks-ip-versioning.txt for details regarding the latter.
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dsifive,gpio.yaml4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
7 title: SiFive GPIO controller
10 - Paul Walmsley <paul.walmsley@sifive.com>
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
19 - const: sifive,gpio0
44 It is 16 for the SiFive SoCs and 32 for the Canaan K210.
69 - sifive,fu540-c000-gpio
70 - sifive,fu740-c000-gpio
79 #include <dt-bindings/clock/sifive-fu540-prci.h>
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
41 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
48 - Paul Walmsley <paul.walmsley@sifive.com>
61 - sifive,fu540-c000-plic
64 - const: sifive,plic-1.0.0
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H A Dsifive,plic-1.0.0.txt1 SiFive Platform-Level Interrupt Controller (PLIC)
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
28 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
31 - compatible : "sifive,plic-1.0.0" and a string identifying the actual
48 compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVProcessors.td86 def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
90 def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
99 def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
109 def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
119 def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
129 def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
139 def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
150 def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
160 def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
170 def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/sifive/
H A Dfu740-prci.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu740-prci.yaml#
8 title: SiFive FU740 Power Reset Clock Interrupt Controller (PRCI)
11 - Zong Li <zong.li@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
18 macros defined in include/dt-bindings/clock/sifive-fu740-prci.h.
27 const: sifive,fu740-c000-prci
59 compatible = "sifive,fu740-c000-prci";
H A Dfu540-prci.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Paul Walmsley <paul.walmsley@sifive.com>
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
26 const: sifive,fu540-c000-prci
55 compatible = "sifive,fu540-c000-prci";
H A Dfu540-prci.txt1 SiFive FU540 PRCI bindings
7 - compatible: Should be "sifive,<chip>-prci". Only one value is
8 supported: "sifive,fu540-c000-prci"
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
42 compatible = "sifive,fu540-c000-prci";
/freebsd/sys/riscv/sifive/
H A Dfiles.sifive2 riscv/sifive/fe310_aon.c optional fe310aon
3 riscv/sifive/fu740_pci_dw.c optional fu740_pci_dw pci fdt
4 riscv/sifive/sifive_gpio.c optional sifive_gpio gpio
5 riscv/sifive/sifive_prci.c standard
6 riscv/sifive/sifive_spi.c optional sifive_spi spibus
7 riscv/sifive/sifive_uart.c standard
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dsifive,fu740-pcie.yaml4 $id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
7 title: SiFive FU740 PCIe host controller
10 SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
16 - Paul Walmsley <paul.walmsley@sifive.com>
17 - Greentime Hu <greentime.hu@sifive.com>
24 const: sifive,fu740-pcie
87 #include <dt-bindings/clock/sifive-fu740-prci.h>
90 compatible = "sifive,fu740-pcie";
/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmicrochip-mpfs.dtsi19 compatible = "sifive,e51", "sifive,rocket0", "riscv";
37 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
91 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
118 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
156 compatible = "sifive,fu540-c000-ccache", "cache";
168 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
178 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
/freebsd/sys/riscv/conf/
H A Dstd.sifive2 # SiFive SoC support
13 makeoptions MODULES_EXTRA+="dtb/sifive"
15 files "../sifive/files.sifive"

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