Searched full:scalers (Results 1 – 17 of 17) sorted by relevance
29 MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System34 * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
414 /** @n_scalers: the number of scaler on @scalers */416 /** @scalers: the pipeline scalers */417 struct komeda_scaler *scalers[KOMEDA_PIPELINE_MAX_SCALERS]; member
392 err = komeda_scaler_obj_add(kms, pipe->scalers[j]); in komeda_kms_add_private_objs()
98 pos = to_cpos(pipe->scalers[id - KOMEDA_COMPONENT_SCALER0]); in komeda_pipeline_get_component_pos()
28 n_scalers:2, /* number of scalers per pipeline */
14 devices are codecs, scalers, deinterlacers or format converters (i.e.
1645 not used during the decoding process but might be used by HW scalers to1650 not used during the decoding process but might be used by HW scalers to
22 R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
74 compiz result to two parts and then feed them to two scalers.385 parts and handles it by two layers and two scalers individually. But it
686 * >= 0 : using a scalers744 struct intel_scaler scalers[SKL_NUM_SCALERS]; member747 * scaler_users: keeps track of users requesting scalers on this crtc.759 * intel_atomic_setup_scalers will setup available scalers to users760 * requesting scalers. It will gracefully fail if request exceeds1519 /* scalers available on this crtc */
6656 /* on skylake this is done by detaching scalers */ in intel_pipe_fastset()
161 /* number of phases supported by the polyphase scalers */
140 /* Disable Scalers */ in meson_vpp_init()
215 HDMI receivers, scalers, deinterlacers.
815 // TODO: QSEED2 and RGB scalers are not yet supported in dpu_rm_try_sspp()
1151 …dml_print("DML: Tsw: %fus = time to fetch enough pixel data and cursor data to feed the scalers i… in CalculatePrefetchSchedule()
1516 …dml_print("DML: Tsw: %fus = time to fetch enough pixel data and cursor data to feed the scalers in… in CalculatePrefetchSchedule()