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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dbrcm,spi-bcm-qspi.txt1 Broadcom SPI controller
3 The Broadcom SPI controller is a SPI master found on various SOCs, including
4 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
6 MSPI : SPI master controller can read and write to a SPI slave device
7 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
14 use SPI protocol.
19 Must be <1>, as required by generic SPI binding.
22 Must be <0>, also as required by generic SPI binding.
26 "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs
27 "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI
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H A Dbrcm,spi-bcm-qspi.yaml4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
7 title: Broadcom SPI controller
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
18 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
25 use SPI protoco
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H A Dmediatek,spi-mt65xx.yaml4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
13 - $ref: /schemas/spi/spi-controller.yaml#
20 - mediatek,mt7629-spi
21 - mediatek,mt8365-spi
22 - const: mediatek,mt7622-spi
25 - mediatek,mt8516-spi
26 - const: mediatek,mt2712-spi
29 - mediatek,mt6779-spi
30 - mediatek,mt8186-spi
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H A Dspi-mt65xx.txt1 Binding for MTK SPI controller
5 - mediatek,mt2701-spi: for mt2701 platforms
6 - mediatek,mt2712-spi: for mt2712 platforms
7 - mediatek,mt6589-spi: for mt6589 platforms
8 - mediatek,mt6765-spi: for mt6765 platforms
9 - mediatek,mt7622-spi: for mt7622 platforms
10 - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
11 - mediatek,mt8135-spi: for mt8135 platforms
12 - mediatek,mt8173-spi: for mt8173 platforms
13 - mediatek,mt8183-spi: for mt8183 platforms
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H A Dsnps,dw-apb-ssi.yaml4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
13 - $ref: spi-controller.yaml#
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
44 const: amd,pensando-elba-spi
55 - description: Generic DW SPI Controller
59 - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
62 - mscc,ocelot-spi
63 - mscc,jaguar2-spi
65 - description: Microchip Sparx5 SoC SPI Controller
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H A Dqcom,spi-qup.txt1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
23 address on the SPI bus. Should be set to 1.
27 - spi-max-frequency: Specifies maximum SPI clock frequency,
29 Documentation/devicetree/bindings/spi/spi-bus.txt
32 The gpios will be referred to as reg = <index> in the SPI child
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H A Dspi-samsung.txt1 * Samsung SPI Controller
3 The Samsung SPI controller is used to interface with various devices such as flash
4 and display controllers using the SPI communication interface.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
27 - clocks: specifies the clock IDs provided to the SPI controller; they are
32 the devices the names must be "spi", "spi_busclkN" (where N is determined by
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H A Dspi-rockchip.yaml4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
7 title: Rockchip SPI Controller
10 The Rockchip SPI controller is used to interface with various devices such
11 as flash and display controllers using the SPI communication interface.
14 - $ref: spi-controller.yaml#
23 - const: rockchip,rk3036-spi
24 - const: rockchip,rk3066-spi
25 - const: rockchip,rk3228-spi
26 - const: rockchip,rv1108-spi
29 - rockchip,px30-spi
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H A Dallwinner,sun6i-a31-spi.yaml4 $id: http://devicetree.org/schemas/spi/allwinner,sun6i-a31-spi.yaml#
7 title: Allwinner A31 SPI Controller
10 - $ref: spi-controller.yaml
19 - const: allwinner,sun50i-r329-spi
20 - const: allwinner,sun6i-a31-spi
21 - const: allwinner,sun8i-h3-spi
24 - allwinner,sun8i-r40-spi
25 - allwinner,sun50i-h6-spi
26 - allwinner,sun50i-h616-spi
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H A Dspi-controller.yaml4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
7 title: SPI Controller Common Properties
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
49 cs-gpio with the optional spi-cs-high flag for SPI slaves.
56 spi-cs-high | - | H |
58 spi-cs-high | ACTIVE_HIGH | H |
60 spi-cs-high | ACTIVE_LOW | H | 2
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H A Dsamsung,spi.yaml4 $id: http://devicetree.org/schemas/spi/samsung,spi.yaml#
7 title: Samsung S3C/S5P/Exynos SoC SPI controller
13 All the SPI controller nodes should be represented in the aliases node using
14 the following format 'spi{n}' where n is a unique number for the alias.
20 - google,gs101-spi
21 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
22 - samsung,s3c6410-spi
23 - samsung,s5pv210-spi # for S5PV210 and S5PC110
24 - samsung,exynos4210-spi
25 - samsung,exynos5433-spi
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H A Dnvidia,tegra114-spi.txt1 NVIDIA Tegra114 SPI controller.
4 - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5 Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
10 - spi
14 - spi
24 - spi-max-frequency: Definition as per
25 Documentation/devicetree/bindings/spi/spi-bus.txt
29 Tegra SPI master with respect to outgoing Tegra SPI master clock.
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H A Dspi-davinci.txt1 Davinci SPI controller device bindings
10 address on the SPI bus. Should be set to 1.
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
20 - ti,davinci-spi-intr-line: interrupt line used to connect the SPI
26 - clocks: spi clk phandle
35 and an args specifier containing the SPI device id
45 SPI slave nodes can contain the following properties.
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H A Dspi-fsl-lpspi.yaml4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
7 title: Freescale Low Power SPI (LPSPI) for i.MX
15 - $ref: /schemas/spi/spi-controller.yaml#
21 - fsl,imx7ulp-spi
22 - fsl,imx8qxp-spi
25 - fsl,imx8ulp-spi
26 - fsl,imx93-spi
27 - fsl,imx95-spi
28 - const: fsl,imx7ulp-spi
37 - description: SoC SPI per clock
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H A Dspi-peripheral-props.yaml4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
32 spi-cs-high:
37 spi-lsb-first:
42 spi-max-frequency:
45 Maximum SPI clocking speed of the device in Hz.
47 spi-cs-setup-delay-ns:
52 spi-cs-hold-delay-ns:
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H A Dspi-lantiq-ssc.txt1 Lantiq Synchronous Serial Controller (SSC) SPI master driver
4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
25 spi: spi@e100800 {
26 compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
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H A Dspi-sifive.yaml4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
7 title: SiFive SPI controller
15 - $ref: spi-controller.yaml#
21 - sifive,fu540-c000-spi
22 - sifive,fu740-c000-spi
26 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
28 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
30 for the SiFive SPI v0 IP block with no chip integration tweaks.
33 SPI RTL that corresponds to the IP block version numbers can be found here -
34 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
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H A Dingenic,spi.yaml4 $id: http://devicetree.org/schemas/spi/ingenic,spi.yaml#
7 title: Ingenic SoCs SPI controller
14 - $ref: /schemas/spi/spi-controller.yaml#
20 - ingenic,jz4750-spi
21 - ingenic,jz4775-spi
22 - ingenic,jz4780-spi
23 - ingenic,x1000-spi
24 - ingenic,x2000-spi
27 - ingenic,jz4760-spi
28 - ingenic,jz4770-spi
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H A Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
4 memory register, which acts as an SPI master device.
17 - compatible: should be "icpdas,lp8841-spi-rtc"
21 Requirements to SPI slave nodes:
25 - The spi slave node should claim the following flags which are
26 required by the spi controller.
28 - spi-3wire: The master itself has only 3 wire. It cannor work in
31 - spi-cs-high: DS-1302 has active high chip select line. The master
34 - spi-lsb-first: DS-1302 requires least significant bit first
40 spi@901c {
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H A Dqcom,spi-geni-qcom.txt1 GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
7 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
11 - compatible: Must contain "qcom,geni-spi".
12 - reg: Must contain SPI register location and length.
13 - interrupts: Must contain SPI controller interrupts.
17 the SPI bus.
20 SPI Controller nodes must be child of GENI based Qualcomm Universal
24 SPI slave nodes must be children of the SPI master node and conform to SPI bus
25 binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
27 mpp3 3 gpo, nand(io5), spi(miso)
30 mpp6 6 sysrst(out), spi(mosi), ptp(trig)
31 mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
36 mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
37 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
62 mpp0 0 gpio, nand(io2), spi(cs)
63 mpp1 1 gpo, nand(io3), spi(mosi)
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dqca,qca7000.txt4 be configured either as SPI or UART slave. This configuration is done by
7 (a) Ethernet over SPI
9 In order to use the QCA7000 as SPI device it must be defined as a child of a
10 SPI master in the device tree.
14 - reg : Should specify the SPI chip select
18 - spi-cpha : Must be set
19 - spi-cpol : Must be set
22 - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at.
24 are invalid. Missing the property will set the SPI
26 - qca,legacy-mode : Set the SPI data transfer of the QCA7000 to legacy mode.
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1028a-qds.dts152 compatible = "jedec,spi-nor";
153 spi-cpol;
154 spi-cpha;
156 spi-max-frequency = <10000000>;
162 compatible = "jedec,spi-nor";
163 spi-cpol;
164 spi-cpha;
166 spi-max-frequency = <10000000>;
172 compatible = "jedec,spi-nor";
173 spi-cpol;
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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Daspeed-smc.txt2 * Aspeed SPI Flash Memory Controller
5 three chip selects, two of which are always of SPI type and the third
6 can be SPI or NOR type flash. These bindings only describe SPI.
8 The two SPI flash memory controllers in the AST2500 each support two
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
27 The child nodes are the SPI flash modules which must have a compatible
28 property as specified in bindings/mtd/jedec,spi-nor.txt
30 Optionally, the child node can contain properties for SPI mode (may be
32 - spi-max-frequency - max frequency of spi bus
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/freebsd/sys/contrib/device-tree/Bindings/tpm/
H A Dtcg,tpm_tis-spi.yaml4 $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml#
7 title: SPI-attached Trusted Platform Module conforming to TCG TIS specification
15 one of them being SPI. The standard is named:
25 - st,st33htpm-spi
26 - st,st33zp24-spi
27 - const: tcg,tpm_tis-spi
31 - $ref: /schemas/spi/spi-peripheral-props.yaml#
36 const: st,st33zp24-spi
39 spi-max-frequency:
50 spi {
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