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/freebsd/sys/dev/ichsmb/
H A Dichsmb_pci.c41 * Support for the SMBus controller logical device which is part of the
62 #include <dev/smbus/smbconf.h>
122 PCI_DESCR("Intel 82801AA (ICH) SMBus controller") },
124 PCI_DESCR("Intel 82801AB (ICH0) SMBus controller") },
126 PCI_DESCR("Intel 82801BA (ICH2) SMBus controller") },
128 PCI_DESCR("Intel 82801CA (ICH3) SMBus controller") },
130 PCI_DESCR("Intel 82801DC (ICH4) SMBus controller") },
132 PCI_DESCR("Intel 82801EB (ICH5) SMBus controller") },
134 PCI_DESCR("Intel 82801FB (ICH6) SMBus controller") },
136 PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") },
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/freebsd/usr.sbin/smbmsg/
H A Dsmbmsg.830 .Nd "send or receive messages over an SMBus"
49 SMBus, see
50 .Xr smbus 4 .
57 the devices on the SMBus.
77 For example, if a particular SMBus device considers
84 This might be useful to explore individual devices on the SMBus, or
96 Since the low-order bit of the device address of SMBus devices
107 from the SMBus device.
114 each individual byte read from the SMBus.
118 byte to be issued as part of the SMBus message.
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/freebsd/sys/dev/imcsmb/
H A Dimcsmb.c49 #include <dev/smbus/smbconf.h>
58 /* SMBus methods */
71 * parent imcsmb_pci's registers that we will use. Create the smbus(4) device,
72 * which any SMBus slave device drivers will connect to.
91 /* Create the smbus child */ in imcsmb_attach()
92 sc->smbus = device_add_child(dev, "smbus", DEVICE_UNIT_ANY); in imcsmb_attach()
93 if (sc->smbus == NULL) { in imcsmb_attach()
95 device_printf(dev, "Child smbus not added\n"); in imcsmb_attach()
100 /* Attach the smbus child. */ in imcsmb_attach()
121 device_set_desc(dev, "iMC SMBus controller"); in imcsmb_probe()
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H A Dimcsmb_pci.c47 #include <dev/smbus/smbconf.h>
54 * SMBus controllers. These are used for reading SPD data from the DIMMs, and
55 * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers
57 * full-fledged SMBus controllers, like the one in Intel ICHs and PCHs.
59 * The publicly available documentation for the iMC SMBus controllers can be
73 * The iMC SMBus controllers do not support interrupts (thus, they must be
78 * Because there are multiple SMBus controllers sharing the same PCI device,
81 * - "imcsmb" is an smbus(4)-compliant SMBus controller driver
88 * firmware. Therefore, when this driver accesses these SMBus controllers, the
97 * over the SMBus. In that case, the NVDIMM driver would be an SMBus slave
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/freebsd/share/man/man4/
H A Dimcsmb.431 .Nd Intel integrated Memory Controller (iMC) SMBus controller driver
34 .Cd device smbus
47 .Xr smbus 4
48 support for the SMBus controller functionality in the integrated Memory
52 each iMC implements two SMBus controllers (iMC-SMBs).
60 general-purpose SMBus controllers.
62 the SMBus operations need for communicating with DIMMs.
108 .Xr smbus 4
111 However, since the IMC-SMBs are not general-purpose SMBus controllers, using
118 .Xr smbus 4
H A Dsmbus.429 .Nm smbus
32 .Cd "device smbus"
37 .Em smbus
52 With the SMBus, a device can provide manufacturer information, tell the
57 The SMBus may share the same host device and physical bus as ACCESS bus
65 .%T The SMBus specification
66 .%U http://www.smbus.org/specs/
H A Diicsmb.432 .Nd I2C to SMBus bridge
36 For one or more smbus busses:
37 .Cd "device smbus"
44 .Xr smbus 4
47 .Xr smbus 4
H A Dsmb.435 .Nd System Management Bus (SMBus) generic I/O device driver
42 .Xr smbus 4
78 SMBus slave device.
115 Note that the SMBus byte-order is little-endian by definition.
151 The SMBus specification mandates that no more than 32 bytes of
186 SMBus transaction timed out.
190 .Xr smbus 4
H A Dismt.439 .Nd Intel SMBus Message Transport (SMBus 2.0) driver
42 .Cd device smbus
46 This driver provides access to the SMBus 2.0 controller device contained
51 .Xr smbus 4
H A Dichsmb.440 .Nd Intel ICH SMBus controller driver
43 .Cd device smbus
50 .Xr smbus 4
51 support for the SMBus controller logical device contained in all Intel
57 .Xr smbus 4
H A Damdpm.433 .Cd device smbus
39 Currently, only the SMBus 1.0 controller function is implemented.
40 The SMBus 2.0 functionality of the AMD 8111 controller is supported via the
44 The embedded SMBus controller of the AMD 756 chipset may give you access
54 .Xr smbus 4
H A Djedec_dimm.436 .Cd "device smbus"
67 .Xr smbus 4 .
100 .Xr smbus 4
103 the SMBus address of the SPD.
107 Since the least-significant bit of an SMBus address is the read/write bit, and
127 .Xr smbus 4 .
207 .Xr smbus 4 ,
H A Dnfsmb.430 .Nd "NVIDIA nForce2/3/4 SMBus 2.0 controller driver"
32 .Cd "device smbus"
38 driver provides access to NVIDIA nForce2/3/4 SMBus 2.0 controllers.
41 .Xr smbus 4
H A Damdsmb.430 .Nd "AMD-8111 SMBus 2.0 controller driver"
33 .Cd "device smbus"
39 driver provides access to the AMD-8111 SMBus 2.0 controller.
44 .Xr smbus 4
H A Dalpm.432 .Cd device smbus
38 Currently, only smbus controller
41 The embedded SMBus controller of the Aladdin chipset may give you access
49 .Xr smbus 4
/freebsd/sys/dev/ipmi/
H A Dipmi_ssif.c39 #include <dev/smbus/smbconf.h>
40 #include <dev/smbus/smb.h>
75 device_t smbus = sc->ipmi_ssif_smbus; in ssif_polled_request() local
81 if (smbus_request_bus(smbus, dev, SMB_WAIT) != 0) in ssif_polled_request()
100 error = smbus_error(smbus_bwrite(smbus, in ssif_polled_request()
115 error = smbus_error(smbus_bwrite(smbus, in ssif_polled_request()
133 error = smbus_error(smbus_bwrite(smbus, in ssif_polled_request()
160 error = smbus_error(smbus_bwrite(smbus, in ssif_polled_request()
174 smbus_release_bus(smbus, dev); in ssif_polled_request()
181 if (smbus_request_bus(smbus, dev, SMB_WAIT) != 0) in ssif_polled_request()
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H A Dipmi_smbus.c40 #include <dev/smbus/smbconf.h>
41 #include <dev/smbus/smbus.h>
42 #include <dev/smbus/smb.h>
130 DRIVER_MODULE(ipmi_smbus, smbus, ipmi_smbus_driver, 0, 0);
131 MODULE_DEPEND(ipmi_smbus, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
/freebsd/sys/dev/iicbus/
H A Diicsmb.c37 * smbus
60 #include <dev/smbus/smb.h>
61 #include <dev/smbus/smbconf.h>
80 device_t smbus; member
111 /* smbus interface */
144 device_set_desc(dev, "SMBus over I2C bridge"); in iicsmb_probe()
155 sc->smbus = device_add_child(dev, "smbus", DEVICE_UNIT_ANY); in iicsmb_attach()
157 /* probe and attach the smbus */ in iicsmb_attach()
192 /* call smbus intr handler */ in iicsmb_intr()
193 smbus_intr(sc->smbus, sc->devaddr, in iicsmb_intr()
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/freebsd/sys/dev/intpm/
H A Dintpm.c36 #include <dev/smbus/smbconf.h>
52 device_t smbus; member
93 { 0x71138086, "Intel PIIX4 SMBUS Interface" },
94 { 0x719b8086, "Intel PIIX4 SMBUS Interface" },
99 { 0x43721002, "ATI IXP400 SMBus Controller" },
100 { AMDSB_SMBUS_DEVID, "AMD SB600/7xx/8xx/9xx SMBus Controller" },
101 { AMDFCH_SMBUS_DEVID, "AMD FCH SMBus Controller" },
102 { AMDCZ_SMBUS_DEVID, "AMD FCH SMBus Controller" },
103 { HYGONCZ_SMBUS_DEVID, "Hygon FCH SMBus Controller" },
152 * w/ SMBus PCI revision ID 0x51 or greater. MMIO is supported on in sb8xx_attach()
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/freebsd/sys/dev/jedec_dimm/
H A Djedec_dimm.c47 #include <dev/smbus/smbconf.h>
48 #include <dev/smbus/smbus.h>
54 device_t smbus; member
55 uint8_t spd_addr; /* SMBus address of the SPD EEPROM. */
228 rc = smbus_writeb(sc->smbus, (JEDEC_DTI_PAGE | JEDEC_LSA_PAGE_SET1), in jedec_dimm_adjust_offset()
283 sc->smbus = device_get_parent(dev); in jedec_dimm_attach()
292 rc = smbus_readb(sc->smbus, sc->spd_addr, SPD_OFFSET_DRAM_TYPE, &byte); in jedec_dimm_attach()
363 rc = smbus_readb(sc->smbus, sc->spd_addr, tsod_present_offset, &byte); in jedec_dimm_attach()
520 rc = smbus_readb(sc->smbus, sc->spd_addr, bus_width_offset, in jedec_dimm_capacity()
527 rc = smbus_readb(sc->smbus, sc->spd_addr, dimm_ranks_offset, in jedec_dimm_capacity()
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/freebsd/sys/modules/i2c/smbus/
H A DMakefile1 .PATH: ${SRCTOP}/sys/dev/smbus
2 KMOD = smbus
4 smbconf.h smbconf.c smbus.h smbus.c
/freebsd/sys/dev/nfsmb/
H A Dnfsmb.c42 #include <dev/smbus/smbconf.h>
75 * ACPI 3.0, Chapter 12, SMBus Host Controller Interface.
116 device_t smbus; member
137 device_set_desc(dev, "nForce2/3/4 MCP SMBus Controller"); in nfsmbsub_probe()
166 device_set_desc(dev, "nForce2/3/4 MCP SMBus Controller"); in nfsmb_probe()
199 nfsmbsub_sc->smbus = device_add_child(dev, "smbus", DEVICE_UNIT_ANY); in nfsmbsub_attach()
200 if (nfsmbsub_sc->smbus == NULL) { in nfsmbsub_attach()
234 /* Allocate a new smbus device */ in nfsmb_attach()
235 nfsmb_sc->smbus = device_add_child(dev, "smbus", DEVICE_UNIT_ANY); in nfsmb_attach()
236 if (!nfsmb_sc->smbus) { in nfsmb_attach()
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/freebsd/sys/dev/amdsmb/
H A Damdsmb.c42 #include <dev/smbus/smbconf.h>
69 * ACPI 3.0, Chapter 12, SMBus Host Controller Interface.
110 device_t smbus; member
127 PCI_DESCR("AMD-8111 SMBus 2.0 Controller") }
161 /* Allocate a new smbus device */ in amdsmb_attach()
162 amdsmb_sc->smbus = device_add_child(dev, "smbus", DEVICE_UNIT_ANY); in amdsmb_attach()
163 if (!amdsmb_sc->smbus) { in amdsmb_attach()
215 device_printf(sc->smbus, "timeout waiting for IBF to clear\n"); in amdsmb_ec_wait_write()
229 device_printf(sc->smbus, "timeout waiting for OBF to set\n"); in amdsmb_ec_wait_read()
552 /* SMBus interface */
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/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-asrock-x570d4u.dts160 /* SMBus on auxiliary panel header (AUX_PANEL1) */
165 /* Hardware monitoring SMBus */
175 /* PSU SMBus (PSU_SMB1) */
193 /* SMBus on PCI express 16x slot */
200 /* SMBus on PCI express 8x slot */
214 /* SMBus on PCI express 1x slot */
223 /* SMBus on BMC connector (BMC_SMB_1) */
228 /* FRU and SPD EEPROM SMBus */
249 /* SMBus on intelligent platform management bus header (IPMB_1) */
/freebsd/sys/dev/alpm/
H A Dalpm.c46 #include <dev/smbus/smbconf.h>
63 #define SMBSTS 0x0 /* SMBus host/slave status register */
64 #define SMBCMD 0x1 /* SMBus host/slave command register */
90 /* SMBus commands */
126 device_t smbus; member
220 /* attach the smbus */ in alpm_attach()
221 alpm->smbus = device_add_child(dev, "smbus", DEVICE_UNIT_ANY); in alpm_attach()
222 if (alpm->smbus == NULL) { in alpm_attach()
298 * Poll the SMBus controller
307 /* wait for command to complete and SMBus controller is idle */ in alpm_wait()
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