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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,sm8450-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
17 See also: include/dt-bindings/interconnect/qcom,sm8450.h
22 - qcom,sm8450-aggre1-noc
23 - qcom,sm8450-aggre2-noc
24 - qcom,sm8450-clk-virt
25 - qcom,sm8450-config-noc
26 - qcom,sm8450-gem-noc
27 - qcom,sm8450-lpass-ag-noc
28 - qcom,sm8450-mc-virt
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm8450-mdss.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
7 title: Qualcomm SM8450 Display MDSS
13 SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
20 const: qcom,sm8450-mdss
45 const: qcom,sm8450-dpu
54 - const: qcom,sm8450-dp
64 - const: qcom,sm8450-dsi-ctrl
73 const: qcom,sm8450-dsi-phy-5nm
82 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
83 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm8450-tlmm.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
7 title: Qualcomm Technologies, Inc. SM8450 TLMM block
13 Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC.
20 const: qcom,sm8450-tlmm
38 - $ref: "#/$defs/qcom-sm8450-tlmm-state"
41 $ref: "#/$defs/qcom-sm8450-tlmm-state"
45 qcom-sm8450-tlmm-state:
106 compatible = "qcom,sm8450-tlmm";
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8450-camcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
7 title: Qualcomm Camera Clock & Reset Controller on SM8450
16 domains on SM8450.
21 include/dt-bindings/clock/qcom,sm8450-camcc.h
32 - qcom,sm8450-camcc
86 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
90 compatible = "qcom,sm8450-camcc";
H A Dqcom,sm8450-videocc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
7 title: Qualcomm Video Clock & Reset Controller on SM8450
15 domains on SM8450.
22 include/dt-bindings/clock/qcom,sm8450-videocc.h
34 - qcom,sm8450-videocc
85 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
89 compatible = "qcom,sm8450-videocc";
H A Dqcom,sm8450-gpucc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM8450
25 include/dt-bindings/clock/qcom,sm8450-gpucc.h
27 include/dt-bindings/reset/qcom,sm8450-gpucc.h
42 - qcom,sm8450-gpucc
88 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
96 compatible = "qcom,sm8450-gpucc";
H A Dqcom,rpmhcc.yaml45 - qcom,sm8450-rpmh-clk
/linux/include/dt-bindings/clock/
H A Dqcom,sm8650-videocc.h9 #include "qcom,sm8450-videocc.h"
11 /* SM8650 introduces below new clocks and resets compared to SM8450 */
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml46 - qcom,sm8450-qmp-gen3x1-pcie-phy
47 - qcom,sm8450-qmp-gen4x2-pcie-phy
179 - qcom,sm8450-qmp-gen3x1-pcie-phy
180 - qcom,sm8450-qmp-gen3x2-pcie-phy
260 - qcom,sm8450-qmp-gen4x2-pcie-phy
H A Dqcom,sc8280xp-qmp-ufs-phy.yaml58 - qcom,sm8450-qmp-ufs-phy
128 - qcom,sm8450-qmp-ufs-phy
/linux/drivers/interconnect/qcom/
H A Dsm8450.c13 #include <dt-bindings/interconnect/qcom,sm8450.h>
1795 { .compatible = "qcom,sm8450-aggre1-noc",
1797 { .compatible = "qcom,sm8450-aggre2-noc",
1799 { .compatible = "qcom,sm8450-clk-virt",
1801 { .compatible = "qcom,sm8450-config-noc",
1803 { .compatible = "qcom,sm8450-gem-noc",
1805 { .compatible = "qcom,sm8450-lpass-ag-noc",
1807 { .compatible = "qcom,sm8450-mc-virt",
1809 { .compatible = "qcom,sm8450-mmss-noc",
1811 { .compatible = "qcom,sm8450-nsp-noc",
[all …]
/linux/drivers/clk/qcom/
H A DMakefile164 obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
176 obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
189 obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
202 obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
216 obj-$(CONFIG_SM_VIDEOCC_8450) += videocc-sm8450.o
H A Dvideocc-sm8450.c11 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
449 { .compatible = "qcom,sm8450-videocc" },
474 .name = "video_cc-sm8450",
481 MODULE_DESCRIPTION("QTI VIDEOCC SM8450 / SM8475 Driver");
H A Dgpucc-sm8450.c11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
765 { .compatible = "qcom,sm8450-gpucc" },
799 .name = "sm8450-gpucc",
805 MODULE_DESCRIPTION("QTI GPU_CC SM8450 / SM8475 Driver");
H A DKconfig1434 tristate "SM8450 Camera Clock Controller"
1439 Support for the camera clock controller on SM8450 or SM8475 devices.
1560 tristate "SM8450 Display Clock Controller"
1566 SM8450 or SM8475 devices.
1694 tristate "SM8450 Global Clock Controller"
1699 Support for the global clock controller on SM8450 or SM8475
1825 tristate "SM8450 Graphics Clock Controller"
1830 Support for the graphics clock controller on SM8450 or SM8475
2044 tristate "SM8450 Video Clock Controller"
2051 SM8450 or SM8475 devices.
/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-wsa-macro.yaml18 - qcom,sm8450-lpass-wsa-macro
72 - qcom,sm8450-lpass-wsa-macro
H A Dqcom,lpass-rx-macro.yaml19 - qcom,sm8450-lpass-rx-macro
109 - qcom,sm8450-lpass-rx-macro
H A Dqcom,lpass-tx-macro.yaml19 - qcom,sm8450-lpass-tx-macro
96 - qcom,sm8450-lpass-tx-macro
H A Dqcom,lpass-va-macro.yaml19 - qcom,sm8450-lpass-va-macro
141 - qcom,sm8450-lpass-va-macro
H A Dqcom,sm8250.yaml34 - const: qcom,sm8450-sndcard
55 - qcom,sm8450-sndcard
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8450-sony-xperia-nagara-pdx224.dts9 #include "sm8450-sony-xperia-nagara.dtsi"
13 compatible = "sony,pdx224", "qcom,sm8450";
H A Dsm8450-sony-xperia-nagara-pdx223.dts9 #include "sm8450-sony-xperia-nagara.dtsi"
13 compatible = "sony,pdx223", "qcom,sm8450";
/linux/drivers/pinctrl/qcom/
H A DMakefile77 obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o
78 obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o
H A DKconfig.msm547 tristate "Qualcomm SM8450 pin controller driver"
553 Technologies Inc SM8450 platform.
/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom-ipcc.yaml46 - qcom,sm8450-ipcc

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