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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,sm8450-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
17 See also:: include/dt-bindings/interconnect/qcom,sm8450.h
22 - qcom,sm8450-aggre1-noc
23 - qcom,sm8450-aggre2-noc
24 - qcom,sm8450-clk-virt
25 - qcom,sm8450-config-noc
26 - qcom,sm8450-gem-noc
27 - qcom,sm8450-lpass-ag-noc
28 - qcom,sm8450-mc-virt
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sm8350-pas.yaml7 title: Qualcomm SM8350/SM8450 Peripheral Authentication Service
13 Qualcomm SM8350/SM8450 SoC Peripheral Authentication Service loads and boots
23 - qcom,sm8450-adsp-pas
24 - qcom,sm8450-cdsp-pas
25 - qcom,sm8450-mpss-pas
26 - qcom,sm8450-slpi-pas
67 - qcom,sm8450-adsp-pas
68 - qcom,sm8450-cdsp-pas
69 - qcom,sm8450-slpi-pas
88 - qcom,sm8450-mpss-pas
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm8450-mdss.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
7 title: Qualcomm SM8450 Display MDSS
13 SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
20 const: qcom,sm8450-mdss
45 const: qcom,sm8450-dpu
54 - const: qcom,sm8450-dp
64 - const: qcom,sm8450-dsi-ctrl
73 const: qcom,sm8450-dsi-phy-5nm
82 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
83 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
[all …]
H A Dqcom,sm8450-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
7 title: Qualcomm SM8450 Display DPU
16 const: qcom,sm8450-dpu
57 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
58 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
60 #include <dt-bindings/interconnect/qcom,sm8450.h>
64 compatible = "qcom,sm8450-dpu";
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8450-videocc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
7 title: Qualcomm Video Clock & Reset Controller on SM8450
15 domains on SM8450.
18 include/dt-bindings/clock/qcom,sm8450-videocc.h
24 - qcom,sm8450-videocc
56 - qcom,sm8450-videocc
66 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
70 compatible = "qcom,sm8450-videocc";
H A Dqcom,sm8450-camcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
7 title: Qualcomm Camera Clock & Reset Controller on SM8450
15 domains on SM8450.
19 include/dt-bindings/clock/qcom,sm8450-camcc.h
28 - qcom,sm8450-camcc
66 - qcom,sm8450-camcc
77 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
81 compatible = "qcom,sm8450-camcc";
H A Dqcom,sm8450-gpucc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM8450
18 include/dt-bindings/clock/qcom,sm8450-gpucc.h
20 include/dt-bindings/reset/qcom,sm8450-gpucc.h
28 - qcom,sm8450-gpucc
51 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
59 compatible = "qcom,sm8450-gpucc";
H A Dqcom,sm8450-dispcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8450
14 domains on SM8450.
16 See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
21 - qcom,sm8450-dispcc
65 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
69 compatible = "qcom,sm8450-dispcc";
H A Dqcom,gcc-sm8450.yaml4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8450
14 domains on SM8450
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
20 const: qcom,gcc-sm8450
63 compatible = "qcom,gcc-sm8450";
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm8450-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
18 const: qcom,sm8450-lpass-lpi-pinctrl
38 - $ref: "#/$defs/qcom-sm8450-lpass-state"
41 $ref: "#/$defs/qcom-sm8450-lpass-state"
45 qcom-sm8450-lpass-state:
90 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
H A Dqcom,sm8450-tlmm.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
7 title: Qualcomm Technologies, Inc. SM8450 TLMM block
13 Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC.
20 const: qcom,sm8450-tlmm
38 - $ref: "#/$defs/qcom-sm8450-tlmm-state"
41 $ref: "#/$defs/qcom-sm8450-tlmm-state"
45 qcom-sm8450-tlmm-state:
106 compatible = "qcom,sm8450-tlmm";
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sm8450.yaml4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
7 title: Qualcomm SM8450 PCI Express Root Complex
14 Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
20 - qcom,pcie-sm8450-pcie0
21 - qcom,pcie-sm8450-pcie1
91 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
94 #include <dt-bindings/interconnect/qcom,sm8450.h>
102 compatible = "qcom,pcie-sm8450-pcie0";
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8450-qrd.dts9 #include "sm8450.dtsi"
19 model = "Qualcomm Technologies, Inc. SM8450 QRD";
20 compatible = "qcom,sm8450-qrd", "qcom,sm8450";
380 firmware-name = "qcom/sm8450/adsp.mbn";
385 firmware-name = "qcom/sm8450/cdsp.mbn";
390 firmware-name = "qcom/sm8450/modem.mbn";
395 firmware-name = "qcom/sm8450/slpi.mbn";
H A Dsm8450.dtsi7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
21 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
292 compatible = "qcom,scm-sm8450", "qcom,scm";
300 compatible = "qcom,sm8450-clk-virt";
306 compatible = "qcom,sm8450-mc-virt";
[all …]
H A Dsm8450-hdk.dts14 #include "sm8450.dtsi"
23 model = "Qualcomm Technologies, Inc. SM8450 HDK";
24 compatible = "qcom,sm8450-hdk", "qcom,sm8450";
95 compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink";
586 firmware-name = "qcom/sm8450/a730_zap.mbn";
873 firmware-name = "qcom/sm8450/adsp.mbn";
878 firmware-name = "qcom/sm8450/cdsp.mbn";
883 firmware-name = "qcom/sm8450/modem.mbn";
888 firmware-name = "qcom/sm8450/slpi.mbn";
912 compatible = "qcom,sm8450-sndcard";
[all …]
/linux/Documentation/devicetree/bindings/ufs/
H A Dqcom,ufs.yaml41 - qcom,sm8450-ufshc
155 - qcom,sm8450-ufshc
294 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
297 #include <dt-bindings/interconnect/qcom,sm8450.h>
305 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml35 - qcom,sm8450-qmp-gen3x1-pcie-phy
36 - qcom,sm8450-qmp-gen4x2-pcie-phy
151 - qcom,sm8450-qmp-gen3x1-pcie-phy
152 - qcom,sm8450-qmp-gen3x2-pcie-phy
223 - qcom,sm8450-qmp-gen4x2-pcie-phy
/linux/include/dt-bindings/clock/
H A Dqcom,sm8650-videocc.h9 #include "qcom,sm8450-videocc.h"
11 /* SM8650 introduces below new clocks and resets compared to SM8450 */
/linux/drivers/interconnect/qcom/
H A DMakefile37 qnoc-sm8450-objs := sm8450.o
74 obj-$(CONFIG_INTERCONNECT_QCOM_SM8450) += qnoc-sm8450.o
H A Dsm8450.c14 #include <dt-bindings/interconnect/qcom,sm8450.h>
19 #include "sm8450.h"
1859 { .compatible = "qcom,sm8450-aggre1-noc",
1861 { .compatible = "qcom,sm8450-aggre2-noc",
1863 { .compatible = "qcom,sm8450-clk-virt",
1865 { .compatible = "qcom,sm8450-config-noc",
1867 { .compatible = "qcom,sm8450-gem-noc",
1869 { .compatible = "qcom,sm8450-lpass-ag-noc",
1871 { .compatible = "qcom,sm8450-mc-virt",
1873 { .compatible = "qcom,sm8450-mmss-noc",
[all …]
/linux/drivers/clk/qcom/
H A DMakefile115 obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
125 obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
136 obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
147 obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
156 obj-$(CONFIG_SM_VIDEOCC_8450) += videocc-sm8450.o
H A DKconfig856 tristate "SM8450 Camera Clock Controller"
860 Support for the camera clock controller on SM8450 devices.
950 tristate "SM8450 Display Clock Controller"
955 SM8450 devices.
1049 tristate "SM8450 Global Clock Controller"
1053 Support for the global clock controller on SM8450 devices.
1148 tristate "SM8450 Graphics Clock Controller"
1152 Support for the graphics clock controller on SM8450 devices.
1280 tristate "SM8450 Video Clock Controller"
1286 SM8450 devices.
/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-wsa-macro.yaml18 - qcom,sm8450-lpass-wsa-macro
68 - qcom,sm8450-lpass-wsa-macro
H A Dqcom,lpass-rx-macro.yaml18 - qcom,sm8450-lpass-rx-macro
88 - qcom,sm8450-lpass-rx-macro
/linux/drivers/pinctrl/qcom/
H A Dpinctrl-sm8450-lpass-lpi.c198 .compatible = "qcom,sm8450-lpass-lpi-pinctrl",
207 .name = "qcom-sm8450-lpass-lpi-pinctrl",
215 MODULE_DESCRIPTION("QTI SM8450 LPI GPIO pin control driver");

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