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Searched full:sgis (Results 1 – 16 of 16) sorted by relevance

/linux/include/kvm/
H A Darm_vgic.h122 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
148 u8 source; /* GICv2 SGIs only */
149 u8 active_source; /* GICv2 SGIs only */
264 /* Wants SGIs without active state */
/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c121 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_write_v3_misc()
131 /* Switching HW SGIs? */ in vgic_mmio_write_v3_misc()
180 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_uaccess_write_v3_misc()
574 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
1034 * An access targeting Group0 SGIs can only generate in vgic_v3_queue_sgi()
1035 * those, while an access targeting Group1 SGIs can in vgic_v3_queue_sgi()
1062 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
1064 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
H A Dvgic.c108 /* SGIs and PPIs */ in vgic_get_vcpu_irq()
606 /* SGIs and LPIs cannot be wired up to any device */ in kvm_vgic_set_owner()
782 /* GICv2 SGIs can count for more than one... */ in compute_ap_list_depth()
814 * If we have multi-SGIs in the pipeline, we need to in vgic_flush_lr_state()
H A Dvgic-mmio.c323 * GICv2 SGIs are terribly broken. We can't restore in __set_pending()
409 * More fun with GICv2 SGIs! If we're clearing one of them in __clear_pending()
745 * The configuration cannot be changed for SGIs in general, in vgic_mmio_write_config()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dnvidia,tegra20-ictlr.txt27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
/linux/drivers/irqchip/
H A Dirq-hip04.c122 /* Interrupt configuration for SGIs can't be changed */ in hip04_irq_set_type()
329 /* Get the interrupt number and add 16 to skip over SGIs */ in hip04_irq_domain_xlate()
H A Dirq-gic-common.c110 * Deactivate and disable all SPIs. Leave the PPI and SGIs in gic_dist_config()
H A Dirq-gic-v3.c90 * There are 16 SGIs, though we only actually use 8 in Linux. The other 8 SGIs
760 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
1013 pr_info("Enabling SGIs without active state\n"); in gic_dist_init()
1286 /* Check all the CPUs have capable of sending SGIs to other CPUs */ in gic_cpu_sys_reg_init()
1341 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1469 /* Register all 8 non-secure SGIs */ in gic_smp_init()
H A Dirq-alpine-msi.c35 u32 num_spis; /* The number of SGIs for MSIs */
H A Dirq-gic.c297 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
365 * works because we don't nest SGIs... in gic_handle_irq()
1000 * Now let's migrate and clear any potential SGIs that might be in gic_migrate_target()
1007 * for previously sent SGIs by us to other CPUs either. in gic_migrate_target()
H A Dirq-gic-v3-its.c4370 * There is no notion of affinity for virtual SGIs, at least in its_sgi_set_affinity()
4487 /* Yes, we do want 16 SGIs */ in its_sgi_irq_domain_alloc()
/linux/tools/testing/selftests/kvm/lib/aarch64/
H A Dvgic.c
H A Dgic_v3.c
/linux/tools/testing/selftests/kvm/aarch64/
H A Dvgic_irq.c
/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst280 SGIs and any interrupt with a higher ID than the number of interrupts
/linux/arch/arm64/kvm/
H A Dsys_regs.c490 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, in access_gic_sgi()