Searched full:set0 (Results 1 – 6 of 6) sorted by relevance
190 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()192 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()194 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0); in ipi_set0_regs_init()196 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0); in ipi_set0_regs_init()198 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()200 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()202 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0); in ipi_set0_regs_init()204 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0); in ipi_set0_regs_init()206 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()208 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()[all …]
23 #define SET0 0x08 macro
441 u32 set0; member451 .set0 = 0,461 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),708 ana[0] |= data->ana->set0; in bcm2835_pll_set_rate()
358 * CPLD firmware maps SET0, SET1 and SET2
673 * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
4195 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", in bnx2x_attn_int_deasserted0()