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/linux/Documentation/devicetree/bindings/mmc/
H A Damlogic,meson-mx-sdhc.yaml4 $id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml#
7 title: Amlogic Meson SDHC controller
16 The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC
24 - amlogic,meson8-sdhc
25 - amlogic,meson8b-sdhc
26 - amlogic,meson8m2-sdhc
27 - const: amlogic,meson-mx-sdhc
60 sdhc: mmc@8e00 {
61 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
H A Dvt8500-sdmmc.txt7 - compatible: Should be "wm,wm8505-sdhc".
15 sdhc@d800a000 {
16 compatible = "wm,wm8505-sdhc";
19 clocks = <&sdhc>;
/linux/drivers/mmc/host/
H A Dsdhci-xenon.h11 /* Register Offset of Xenon SDHC self-defined register */
66 /* idx of SDHC */
84 * record the current ios setting of Xenon SDHC.
H A DMakefile66 meson-mx-sdhc-objs := meson-mx-sdhc-clkc.o meson-mx-sdhc-mmc.o
67 obj-$(CONFIG_MMC_MESON_MX_SDHC) += meson-mx-sdhc.o
H A Dmeson-mx-sdhc-clkc.c3 * Amlogic Meson SDHC clock controller
13 #include "meson-mx-sdhc.h"
H A Dsdhci-xenon-phy.c3 * PHY support for Xenon SDHC
449 /* Disable both SDHC Data Strobe and Enhanced Strobe */ in xenon_emmc_phy_disable_strobe()
483 /* Enable SDHC Data Strobe */ in xenon_emmc_phy_strobe_delay_adj()
487 * Enable SDHC Enhanced Strobe if supported in xenon_emmc_phy_strobe_delay_adj()
824 * and adjust Xenon SDHC delay. in xenon_phy_adj()
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8m2.dtsi87 &sdhc {
88 compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc";
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-esdhc-0.dtsi35 sdhc: sdhc@114000 { label
H A Dt102xsi-pre.dtsi59 sdhc = &sdhc;
H A Db4420si-pre.dtsi57 sdhc = &sdhc;
H A Db4860si-pre.dtsi57 sdhc = &sdhc;
H A Dp5020si-pre.dtsi61 sdhc = &sdhc;
H A Dt208xsi-pre.dtsi74 sdhc = &sdhc;
H A Dt104xsi-pre.dtsi58 sdhc = &sdhc;
H A Dp3041si-pre.dtsi61 sdhc = &sdhc;
H A Dp2041si-pre.dtsi60 sdhc = &sdhc;
H A Dp5040si-pre.dtsi60 sdhc = &sdhc;
H A Dp4080si-pre.dtsi60 sdhc = &sdhc;
H A Dt4240si-pre.dtsi64 sdhc = &sdhc;
/linux/arch/arm/boot/dts/vt8500/
H A Dwm8650.dtsi164 clksdhc: sdhc {
194 sdhc@d800a000 {
195 compatible = "wm,wm8505-sdhc";
H A Dwm8505.dtsi192 clksdhc: sdhc {
286 sdhc@d800a000 {
287 compatible = "wm,wm8505-sdhc";
H A Dwm8850.dtsi206 clksdhc: sdhc {
297 sdhc@d800a000 {
298 compatible = "wm,wm8505-sdhc";
H A Dwm8750.dtsi211 clksdhc: sdhc {
326 sdhc@d800a000 {
327 compatible = "wm,wm8505-sdhc";
/linux/Documentation/devicetree/bindings/clock/
H A Dvt8500.txt66 sdhc: sdhc {
/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c746 * the Reference Manual discusses that for SDHC only even divide in mpc512x_clk_setup_clock_tree()
756 clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 2, 1); in mpc512x_clk_setup_clock_tree()
757 clks[MPC512x_CLK_SDHC_UG] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0, in mpc512x_clk_setup_clock_tree()
762 "sdhc2-ug", "sdhc-x4", 0, &clkregs->scfr2, in mpc512x_clk_setup_clock_tree()
866 clks[MPC512x_CLK_SDHC] = mpc512x_clk_gated("sdhc", "sdhc-ug", in mpc512x_clk_setup_clock_tree()
890 "sdhc-2", "sdhc2-ug", &clkregs->sccr2, 17); in mpc512x_clk_setup_clock_tree()

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