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110 (SDER) is accessible. This will cause the driver to do112 state. If not present the ARMv7 SDER will not be touched,
2420 ** 0x59-0x58: Secondary Decode Enable Register - SDER3719 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register.3720 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero3721 ** 1=Private Memory control Enabled - SDER register bits 2 default to one