| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-rockchip.yaml | 110 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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| /linux/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 102 #define SCLK_SPI0 90 macro
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| H A D | exynos7-clk.h | 109 #define SCLK_SPI0 17 macro
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| H A D | s5pv210.h | 193 #define SCLK_SPI0 171 macro
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| H A D | rk3128-cru.h | 20 #define SCLK_SPI0 65 macro
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| H A D | rk3228-cru.h | 18 #define SCLK_SPI0 65 macro
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| H A D | rv1108-cru.h | 17 #define SCLK_SPI0 65 macro
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| H A D | rk3308-cru.h | 31 #define SCLK_SPI0 27 macro
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| H A D | px30-cru.h | 38 #define SCLK_SPI0 36 macro
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| H A D | rk3288-cru.h | 20 #define SCLK_SPI0 65 macro
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| H A D | rk3368-cru.h | 21 #define SCLK_SPI0 65 macro
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| H A D | rk3399-cru.h | 28 #define SCLK_SPI0 71 macro
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | samsung,exynos7-clock.yaml | 155 - const: sclk_spi0
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3128.c | 398 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
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| H A D | clk-rk3228.c | 474 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
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| H A D | clk-rk3368.c | 535 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
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| H A D | clk-rk3288.c | 516 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
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| H A D | clk-rk3308.c | 403 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0,
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| H A D | clk-px30.c | 744 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3xxx.dtsi | 454 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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| H A D | rk322x.dtsi | 424 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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| H A D | rk3128.dtsi | 843 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | s5pv210.dtsi | 158 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
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| /linux/arch/arm64/boot/dts/exynos/ |
| H A D | exynos7.dtsi | 238 "sclk_spi0",
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3368.dtsi | 239 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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