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/linux/drivers/net/wireless/realtek/rtw88/
H A Dsar.c5 #include "sar.h"
12 const struct rtw_sar *sar = &hal->sar; in rtw_query_sar() local
14 switch (sar->src) { in rtw_query_sar()
16 rtw_warn(rtwdev, "unknown SAR source: %d\n", sar->src); in rtw_query_sar()
21 return sar->cfg[arg->path][arg->rs].common[arg->sar_band]; in rtw_query_sar()
28 struct rtw_sar *sar = &hal->sar; in rtw_apply_sar() local
30 if (sar->src != RTW_SAR_SOURCE_NONE && new->src != sar->src) { in rtw_apply_sar()
31 rtw_warn(rtwdev, "SAR source: %d is in use\n", sar->src); in rtw_apply_sar()
35 *sar = *new; in rtw_apply_sar()
41 static s8 rtw_sar_to_phy(struct rtw_dev *rtwdev, u8 fct, s32 sar, in rtw_sar_to_phy() argument
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/linux/drivers/clk/mvebu/
H A Dorion.c28 static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar) in mv88f5181_get_tclk_freq() argument
30 u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & in mv88f5181_get_tclk_freq()
45 static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar) in mv88f5181_get_cpu_freq() argument
47 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & in mv88f5181_get_cpu_freq()
59 static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id, in mv88f5181_get_clk_ratio() argument
62 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & in mv88f5181_get_clk_ratio()
98 static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar) in mv88f5182_get_tclk_freq() argument
100 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) & in mv88f5182_get_tclk_freq()
113 static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar) in mv88f5182_get_cpu_freq() argument
115 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & in mv88f5182_get_cpu_freq()
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H A Dkirkwood.c25 * (6180 has different SAR layout than other Kirkwood SoCs)
86 static u32 __init kirkwood_get_tclk_freq(void __iomem *sar) in kirkwood_get_tclk_freq() argument
88 u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) & in kirkwood_get_tclk_freq()
108 static u32 __init kirkwood_get_cpu_freq(void __iomem *sar) in kirkwood_get_cpu_freq() argument
110 u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar)); in kirkwood_get_cpu_freq()
127 void __iomem *sar, int id, int *mult, int *div) in kirkwood_get_clk_ratio() argument
132 u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar)); in kirkwood_get_clk_ratio()
139 u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) & in kirkwood_get_clk_ratio()
155 static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar) in mv88f6180_get_cpu_freq() argument
157 u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK; in mv88f6180_get_cpu_freq()
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H A Dcommon.h28 u32 (*get_tclk_freq)(void __iomem *sar);
29 u32 (*get_cpu_freq)(void __iomem *sar);
30 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
31 u32 (*get_refclk_freq)(void __iomem *sar);
32 bool (*is_sscg_enabled)(void __iomem *sar);
H A Darmada-39x.c45 static u32 __init armada_39x_get_tclk_freq(void __iomem *sar) in armada_39x_get_tclk_freq() argument
49 tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) & in armada_39x_get_tclk_freq()
68 static u32 __init armada_39x_get_cpu_freq(void __iomem *sar) in armada_39x_get_cpu_freq() argument
72 cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) & in armada_39x_get_cpu_freq()
92 void __iomem *sar, int id, int *mult, int *div) in armada_39x_get_clk_ratio() argument
110 static u32 __init armada_39x_refclk_ratio(void __iomem *sar) in armada_39x_refclk_ratio() argument
112 if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ) in armada_39x_refclk_ratio()
H A Darmada-38x.c20 * SAR[14:10] : Ratios between PCLK0, NBCLK, HCLK and DRAM clocks
22 * SAR[15] : TCLK frequency
37 static u32 __init armada_38x_get_tclk_freq(void __iomem *sar) in armada_38x_get_tclk_freq() argument
41 tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) & in armada_38x_get_tclk_freq()
54 static u32 __init armada_38x_get_cpu_freq(void __iomem *sar) in armada_38x_get_cpu_freq() argument
58 cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) & in armada_38x_get_cpu_freq()
99 void __iomem *sar, int id, int *mult, int *div) in armada_38x_get_clk_ratio() argument
101 u32 opt = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) & in armada_38x_get_clk_ratio()
H A Darmada-370.c45 static u32 __init a370_get_tclk_freq(void __iomem *sar) in a370_get_tclk_freq() argument
49 tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) & in a370_get_tclk_freq()
64 static u32 __init a370_get_cpu_freq(void __iomem *sar) in a370_get_cpu_freq() argument
69 cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) & in a370_get_cpu_freq()
114 void __iomem *sar, int id, int *mult, int *div) in a370_get_clk_ratio() argument
116 u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) & in a370_get_clk_ratio()
135 static bool a370_is_sscg_enabled(void __iomem *sar) in a370_is_sscg_enabled() argument
137 return !(readl(sar) & SARL_A370_SSCG_ENABLE); in a370_is_sscg_enabled()
H A Ddove.c87 static u32 __init dove_get_tclk_freq(void __iomem *sar) in dove_get_tclk_freq() argument
89 u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) & in dove_get_tclk_freq()
106 static u32 __init dove_get_cpu_freq(void __iomem *sar) in dove_get_cpu_freq() argument
108 u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) & in dove_get_cpu_freq()
126 void __iomem *sar, int id, int *mult, int *div) in dove_get_clk_ratio() argument
131 u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) & in dove_get_clk_ratio()
139 u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) & in dove_get_clk_ratio()
H A Dmv98dx3236.c44 static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar) in mv98dx3236_get_tclk_freq() argument
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
68 static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar) in mv98dx3236_get_cpu_freq() argument
73 cpu_freq_select = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) & in mv98dx3236_get_cpu_freq()
118 void __iomem *sar, int id, int *mult, int *div) in mv98dx3236_get_clk_ratio() argument
120 u32 opt = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) & in mv98dx3236_get_clk_ratio()
H A Darmada-375.c50 static u32 __init armada_375_get_tclk_freq(void __iomem *sar) in armada_375_get_tclk_freq() argument
54 tclk_freq_select = ((readl(sar) >> SAR1_A375_TCLK_FREQ_OPT) & in armada_375_get_tclk_freq()
71 static u32 __init armada_375_get_cpu_freq(void __iomem *sar) in armada_375_get_cpu_freq() argument
75 cpu_freq_select = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) & in armada_375_get_cpu_freq()
115 void __iomem *sar, int id, int *mult, int *div) in armada_375_get_clk_ratio() argument
117 u32 opt = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) & in armada_375_get_clk_ratio()
/linux/Documentation/devicetree/bindings/sound/
H A Dnuvoton,nau8824.yaml72 nuvoton,sar-threshold-num:
80 nuvoton,sar-threshold:
84 configuration. SAR value is calculated as
85 SAR = 255 * MICBIAS / SAR_VOLTAGE * R / (2000 + R) where MICBIAS is
87 'nuvoton,sar-voltage', R - button impedance.
96 nuvoton,sar-hysteresis:
102 nuvoton,sar-voltage:
117 nuvoton,sar-compare-time:
120 SAR compare time.
128 nuvoton,sar-sampling-time:
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/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intc_sar7 Specific Absorption Rate (SAR) regulatory mode is typically
11 the current SAR regulatory mode on the Dynamic SAR driver using
14 from the Dynamic SAR driver.
32 This sysfs entry is used to retrieve Dynamic SAR information
33 emitted/maintained by a BIOS that supports Dynamic SAR.
44 level using the Band/Antenna/SAR table index information.
48 given host. The regulatory mode configured on Dynamic SAR
/linux/drivers/net/wireless/intel/iwlwifi/fw/
H A Dregulatory.h19 * Each SAR profile has (up to, depends on the table revision) 4 chains:
66 * struct iwl_sar_profile_chain - per-chain values of a SAR profile
67 * @subbands: the SAR value for each subband
74 * struct iwl_sar_profile - SAR profile from SAR tables
76 * @chains: per-chain SAR values
83 /* Same thing as with SAR, all revisions fit in revision 2 */
86 * struct iwl_geo_profile_band - per-band geo SAR offsets
88 * @chains: SAR offsets values for each chain
97 * @bands: per-band table of the SAR offsets
103 /* Same thing as with SAR, all revisions fit in revision 2 */
/linux/drivers/platform/x86/intel/int1092/
H A DKconfig7 M.2 modem to regulate the RF power based on SAR data obtained from the
9 to SAR driver. The front end application in userspace will interact with SAR
11 SAR table index and use available communication like MBIM interface to enable
13 given platform needs to support "Dynamic SAR" configuration for a modem available
H A Dintel_sar.h25 * @sartable_index: Index of SAR
54 * @bios_table_revision: Version of SAR table
64 * Structure wwan_sar_context - context of SAR
/linux/drivers/bluetooth/
H A Dbtintel.c2981 bt_dev_warn(hdev, "Failed to send sar ddc id:0x%4.4x (%ld)",
2990 int id, struct btintel_sar_inc_pwr *sar)
2994 cmd->data[0] = sar->br >> 3; in btintel_send_edr2()
2995 cmd->data[1] = sar->edr2 >> 3; in btintel_send_edr2()
2996 cmd->data[2] = sar->edr3 >> 3; in btintel_send_edr2()
3001 int id, struct btintel_sar_inc_pwr *sar) in btintel_send_edr3() argument
3005 cmd->data[0] = min3(sar->le, sar->le_lr, sar->le_2mhz) >> 3; in btintel_send_edr3()
3010 int id, struct btintel_sar_inc_pwr *sar) in btintel_set_legacy_sar()
2954 btintel_send_edr(struct hci_dev * hdev,struct btintel_cp_ddc_write * cmd,int id,struct btintel_sar_inc_pwr * sar) btintel_send_edr() argument
2965 btintel_send_le(struct hci_dev * hdev,struct btintel_cp_ddc_write * cmd,int id,struct btintel_sar_inc_pwr * sar) btintel_send_le() argument
2974 btintel_send_br(struct hci_dev * hdev,struct btintel_cp_ddc_write * cmd,int id,struct btintel_sar_inc_pwr * sar) btintel_send_br() argument
2983 btintel_send_br_mutual(struct hci_dev * hdev,struct btintel_cp_ddc_write * cmd,int id,struct btintel_sar_inc_pwr * sar) btintel_send_br_mutual() argument
2992 btintel_send_edr2(struct hci_dev * hdev,struct btintel_cp_ddc_write * cmd,int id,struct btintel_sar_inc_pwr * sar) btintel_send_edr2() argument
3009 btintel_set_legacy_sar(struct hci_dev * hdev,struct btintel_sar_inc_pwr * sar) btintel_set_legacy_sar() argument
3045 btintel_set_mutual_sar(struct hci_dev * hdev,struct btintel_sar_inc_pwr * sar) btintel_set_mutual_sar() argument
3124 btintel_set_sar_rev2(struct hci_dev * hdev,struct btintel_sar_rev2 * sar) btintel_set_sar_rev2() argument
3195 btintel_sar_rev2_send_to_device(struct hci_dev * hdev,struct btintel_sar_rev2 * sar,struct intel_version_tlv * ver) btintel_sar_rev2_send_to_device() argument
3211 btintel_sar_send_to_device(struct hci_dev * hdev,struct btintel_sar_inc_pwr * sar,struct intel_version_tlv * ver) btintel_sar_send_to_device() argument
3236 struct btintel_sar_inc_pwr sar; btintel_acpi_set_sar() local
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/linux/arch/parisc/kernel/
H A Dperf_asm.S154 shrpd ret0,%r0,%sar,%r1
178 shrpd ret0,%r0,%sar,%r1
274 shrpd ret0,%r0,%sar,%r1
286 shrpd ret0,%r0,%sar,%r1
322 shrpd ret0,%r0,%sar,%r1
358 shrpd ret0,%r0,%sar,%r1
370 shrpd ret0,%r0,%sar,%r1
466 shrpd ret0,%r0,%sar,%r1
478 shrpd ret0,%r0,%sar,%r1
514 shrpd ret0,%r0,%sar,%r1
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H A Dsignal32.c98 /* Load the upper half for sar */ in restore_sigcontext32()
100 regs->sar = ((u64)compat_regt << 32) | (u64)compat_reg; in restore_sigcontext32()
101 DBG(2,"restore_sigcontext32: upper_half & sar = %#lx\n", compat_regt); in restore_sigcontext32()
102 DBG(2,"restore_sigcontext32: sar is %#lx\n", regs->sar); in restore_sigcontext32()
238 compat_reg = (compat_uint_t)(regs->sar); in setup_sigcontext32()
240 DBG(2,"setup_sigcontext32: sar is %#x\n", compat_reg); in setup_sigcontext32()
242 compat_reg = (compat_uint_t)(regs->sar >> 32); in setup_sigcontext32()
244 DBG(2,"setup_sigcontext32: upper half sar = %#x\n", compat_reg); in setup_sigcontext32()
/linux/drivers/dma/dw-edma/
H A Ddw-hdma-v0-core.c220 u32 control, u32 size, u64 sar, u64 dar) in dw_hdma_v0_write_ll_data() argument
228 lli->sar.reg = sar; in dw_hdma_v0_write_ll_data()
236 writeq(sar, &lli->sar.reg); in dw_hdma_v0_write_ll_data()
308 SET_CH_32(dw, chan->dir, chan->id, sar.lsb, in dw_hdma_v0_core_non_ll_start()
309 lower_32_bits(child->sar)); in dw_hdma_v0_core_non_ll_start()
310 SET_CH_32(dw, chan->dir, chan->id, sar.msb, in dw_hdma_v0_core_non_ll_start()
311 upper_32_bits(child->sar)); in dw_hdma_v0_core_non_ll_start()
362 dw_hdma_v0_write_ll_data(chan, idx, control, burst->sz, burst->sar, in dw_hdma_v0_core_ll_data()
/linux/arch/sh/drivers/dma/
H A Ddma-g2.c97 if (chan->sar & 31) { in g2_xfer_dma()
98 printk("g2dma: unaligned source 0x%lx\n", chan->sar); in g2_xfer_dma()
117 flush_icache_range((unsigned long)chan->sar, chan->count); in g2_xfer_dma()
122 g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0; in g2_xfer_dma()
136 pr_debug("count, sar, dar, mode, ctrl, chan, xfer: %ld, 0x%08lx, " in g2_xfer_dma()
/linux/Documentation/devicetree/bindings/iio/proximity/
H A Dawinic,aw96103.yaml14 The specific absorption rate (SAR) is a metric that measures
20 power of the antenna to keep the SAR within a safe range. Therefore,
21 we also refer to the proximity sensor as a SAR sensor.
/linux/arch/arm/mach-omap2/
H A Domap4-sar-layout.h3 * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
12 * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
/linux/arch/xtensa/kernel/
H A Dcoprocessor.S152 /* Save remaining registers a1-a3 and SAR */
155 rsr a3, sar
177 /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
179 ssl a3 # SAR: 32 - coprocessor_number
261 wsr a0, sar
/linux/Documentation/devicetree/bindings/input/
H A Diqs62x-keys.yaml72 | 10 | SAR Active*** | x | | x | | |
74 | 11 | SAR Quick Rel.*** | x | | x | | |
76 | 12 | SAR Movement*** | x | | x | | |
78 | 13 | SAR Filter Halt*** | x | | x | | |
84 * Two-channel SAR. Replaces CH0-2 plus metal touch and proximity events
88 *** One-channel SAR. Replaces CH0-2 touch and proximity events if enabled
/linux/drivers/dma/
H A Dtxx9dmac.c287 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x" in txx9dmac_dump_regs()
290 channel64_readq(dc, SAR), in txx9dmac_dump_regs()
299 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x" in txx9dmac_dump_regs()
302 channel32_readl(dc, SAR), in txx9dmac_dump_regs()
316 channel_writeq(dc, SAR, 0); in txx9dmac_reset_chan()
320 channel_writel(dc, SAR, 0); in txx9dmac_reset_chan()
474 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR); in txx9dmac_dump_desc()
479 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR, in txx9dmac_dump_desc()
487 d->CHAR, d->SAR, d->DAR, d->CNTR); in txx9dmac_dump_desc()
492 d->CHAR, d->SAR, d->DAR, d->CNTR, in txx9dmac_dump_desc()
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