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/linux/arch/mips/ath79/
H A Dsetup.c49 u32 rev = 0; in ath79_detect_sys_type() local
58 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; in ath79_detect_sys_type()
59 rev &= AR71XX_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
81 rev = id & AR724X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
87 rev = id & AR724X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
93 rev = id & AR724X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
98 rev = id >> AR913X_REV_ID_REVISION_SHIFT; in ath79_detect_sys_type()
99 rev &= AR913X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
116 rev = id & AR933X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
122 rev = id & AR933X_REV_ID_REVISION_MASK; in ath79_detect_sys_type()
[all …]
/linux/arch/powerpc/kernel/
H A Dcpu_specs_44x.h13 .cpu_name = "440GR Rev. A",
25 .cpu_name = "440EP Rev. A",
38 .cpu_name = "440GR Rev. B",
50 .cpu_name = "440EP Rev. C",
63 .cpu_name = "440EP Rev. B",
99 { /* 440GP Rev. B */
102 .cpu_name = "440GP Rev. B",
111 { /* 440GP Rev. C */
114 .cpu_name = "440GP Rev. C",
123 { /* 440GX Rev. A */
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/linux/arch/arm/mach-s3c/
H A Dmach-crag6410-module.c38 /* Active high for Glenfarclas Rev 2 */
344 u8 rev; member
353 { .id = 0x01, .rev = 0xff, .name = "1250-EV1 Springbank" },
354 { .id = 0x02, .rev = 0xff, .name = "1251-EV1 Jura" },
355 { .id = 0x03, .rev = 0xff, .name = "1252-EV1 Glenlivet" },
356 { .id = 0x06, .rev = 0xff, .name = "WM8997-6721-CS96-EV1 Lapraoig" },
357 { .id = 0x07, .rev = 0xff, .name = "WM5110-6271 Deanston",
360 { .id = 0x08, .rev = 0xff, .name = "WM8903-6102 Tamdhu" },
361 { .id = 0x09, .rev = 0xff, .name = "WM1811A-6305 Adelphi" },
362 { .id = 0x0a, .rev = 0xff, .name = "WM8996-6272 Blackadder" },
[all …]
/linux/arch/arm/mach-omap2/
H A Did.c152 u8 dev_type, rev; in omap2xxx_check_revision() local
158 rev = (idcode >> 28) & 0x0f; in omap2xxx_check_revision()
162 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", in omap2xxx_check_revision()
163 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); in omap2xxx_check_revision()
353 u8 rev; in omap3xxx_check_revision() local
369 * hawkeye and rev. See TRM 1.5.2 Device Identification. in omap3xxx_check_revision()
370 * Note that rev does not map directly to our defined processor in omap3xxx_check_revision()
375 rev = (idcode >> 28) & 0xff; in omap3xxx_check_revision()
380 switch (rev) { in omap3xxx_check_revision()
412 switch (rev) { in omap3xxx_check_revision()
[all …]
/linux/arch/arm/mach-imx/
H A Dcpu-imx31.c21 unsigned int rev; member
23 { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
24 { .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
25 { .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
26 { .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
27 { .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
28 { .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 },
29 { .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 },
30 { .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 },
31 { .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 },
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/linux/drivers/ras/amd/atl/
H A Dreg_fields.h28 * Rev Fieldname Bits
46 * Rev Fieldname Bits
69 * Rev Fieldname Bits
94 * Rev Fieldname Bits
119 * Rev Fieldname Bits
137 * Rev Fieldname Bits
158 * Rev Fieldname Bits
180 * Rev Fieldname Bits
199 * Rev Fieldname Bits
221 * Rev Fieldname Bits
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/linux/arch/powerpc/kvm/
H A Dbook3s_hv_rm_mmu.c68 void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev, in kvmppc_add_revmap_chain() argument
76 head = &kvm->arch.hpt.rev[i]; in kvmppc_add_revmap_chain()
79 tail = &kvm->arch.hpt.rev[head->back]; in kvmppc_add_revmap_chain()
82 rev->forw = i; in kvmppc_add_revmap_chain()
83 rev->back = head->back; in kvmppc_add_revmap_chain()
87 rev->forw = rev->back = pte_index; in kvmppc_add_revmap_chain()
148 struct revmap_entry *rev, in remove_revmap_chain() argument
159 ptel = rev->guest_rpte |= rcbits; in remove_revmap_chain()
166 next = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->forw]); in remove_revmap_chain()
167 prev = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->back]); in remove_revmap_chain()
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/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dmlxsw_lib.sh27 local rev=$1; shift
29 local rev2=${rev%+}
31 if [[ $rev2 != $rev ]]; then
40 local rev=$1; shift
44 if ! mlxsw_on_spectrum "$rev"; then
45 log_test_xfail $src:$caller "(Spectrum-$rev only)"
54 local rev
56 for rev in "$@"; do
57 if __mlxsw_only_on_spectrum "$rev" "$caller" "$src"; then
/linux/sound/soc/codecs/
H A Dtfa989x.c55 unsigned int rev; member
60 const struct tfa989x_rev *rev; member
126 if (tfa989x->rev->rev == TFA9897_REVISION) in tfa989x_probe()
215 .rev = TFA9890_REVISION,
240 .rev = TFA9895_REVISION,
263 .rev = TFA9897_REVISION,
320 const struct tfa989x_rev *rev; in tfa989x_i2c_probe() local
326 rev = device_get_match_data(dev); in tfa989x_i2c_probe()
327 if (!rev) { in tfa989x_i2c_probe()
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/linux/Documentation/devicetree/bindings/gpu/
H A Dimg,powervr-sgx.yaml19 - ti,omap3430-gpu # Rev 121
20 - ti,omap3630-gpu # Rev 125
24 - ingenic,jz4780-gpu # Rev 130
25 - ti,omap4430-gpu # Rev 120
29 - allwinner,sun6i-a31-gpu # MP2 Rev 115
30 - ti,omap4470-gpu # MP1 Rev 112
31 - ti,omap5432-gpu # MP2 Rev 105
32 - ti,am5728-gpu # MP2 Rev 116
33 - ti,am6548-gpu # MP1 Rev 117
/linux/drivers/acpi/
H A Dpci_mcfg.c42 /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
46 #define AL_ECAM(table_id, rev, seg, ops) \ argument
47 { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
86 #define THUNDER_PEM_QUIRK(rev, node) \ argument
87 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
89 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
91 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
93 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
95 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
97 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
[all …]
/linux/arch/arm/include/debug/
H A Dsamsung.S14 ARM_BE8(rev \rd, \rd)
20 ARM_BE8(rev \rd, \rd)
29 ARM_BE8(rev \rd, \rd)
39 ARM_BE8(rev \rd, \rd)
53 ARM_BE8(rev \rd, \rd)
65 ARM_BE8(rev \rd, \rd)
77 ARM_BE8(rev \rd, \rd)
89 ARM_BE8(rev \rd, \rd)
/linux/drivers/net/wireless/broadcom/b43/
H A Dwa.c26 if (phy->rev <= 2) in b43_wa_initgains()
34 if (phy->rev <= 3) in b43_wa_initgains()
36 else if (phy->rev == 5) { in b43_wa_initgains()
40 if (phy->rev >= 3) in b43_wa_initgains()
48 if (0 /* FIXME: For APHY.rev=2 this might be needed */) { in b43_wa_rssi_lt()
87 if (phy->rev == 1) in b43_wa_nft()
117 if (phy->rev >= 6) { in b43_wa_nst()
159 if (phy->rev == 1) { in b43_wa_crs_ed()
161 } else if (phy->rev == 2) { in b43_wa_crs_ed()
192 if (dev->phy.rev == 1) { in b43_wa_wrssi_offset()
[all …]
H A Dphy_n.c164 if (phy->rev >= 19 || phy->rev < 3) { in b43_nphy_rf_ctl_override_rev7()
204 B43_WARN_ON(phy->rev < 7); in b43_nphy_rf_ctl_override_one_to_many()
250 if (dev->phy.rev >= 3) { in b43_nphy_rf_ctl_override()
393 if (dev->phy.rev >= 7) { in b43_nphy_rf_ctl_intc_override()
399 B43_WARN_ON(dev->phy.rev < 3); in b43_nphy_rf_ctl_intc_override()
637 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; in b43_nphy_set_rf_sequence()
739 case 9: /* e.g. PHY rev 16 */ in b43_radio_2057_setup()
1134 B43_WARN_ON(dev->phy.rev < 3); in b43_radio_2056_setup()
1176 if (dev->phy.rev >= 5) { in b43_radio_2056_setup()
1305 if (phy->rev != 3) in b43_radio_2056_rcal()
[all …]
/linux/arch/arm/mach-orion5x/
H A Dcommon.c197 u32 rev, dev; in orion5x_init_early() local
203 orion5x_pcie_id(&dev, &rev); in orion5x_init_early()
249 u32 dev, rev; in orion5x_find_tclk() local
251 orion5x_pcie_id(&dev, &rev); in orion5x_find_tclk()
272 * Identify device ID and rev from PCIe configuration header space '0'.
274 void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) in orion5x_id() argument
276 orion5x_pcie_id(dev, rev); in orion5x_id()
279 if (*rev == MV88F5281_REV_D2) { in orion5x_id()
281 } else if (*rev == MV88F5281_REV_D1) { in orion5x_id()
283 } else if (*rev == MV88F5281_REV_D0) { in orion5x_id()
[all …]
/linux/Documentation/arch/arm/google/
H A Dchromebook-boot-flow.rst18 strappings, perhaps via some other method). This is $(REV) below.
23 - google,$(BOARD)-rev$(REV)-sku$(SKU)
24 - google,$(BOARD)-rev$(REV)
29 not include SKU matching or may prioritize SKU/rev differently.
41 As an example, if we're on board "lazor", rev 4, SKU 0 and we have two device
63 supporting the newest revision(s) of a board omits the "-rev{REV}"
/linux/arch/arm64/lib/
H A Dstrcmp.S71 rev tmp, data1
82 rev has_nul, has_nul
88 rev syndrome, syndrome
89 rev data1, data1
90 rev data2, data2
139 rev data3, data3
156 rev data3, data3
167 rev tmp, tmp
178 rev data2, data2
179 rev has_nul, has_nul
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h30 u32 chipcontrol; /* 0x28, rev >= 11 */
31 u32 chipstatus; /* 0x2c, rev >= 11 */
34 u32 jtagcmd; /* 0x30, rev >= 10 */
199 u32 gpiosel; /* 0x638, rev >= 1 */
200 u32 gpioenable; /* 0x63c, rev >= 1 */
252 #define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
253 #define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */
254 /* Nand flash present, rev >= 35 */
257 #define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
258 /* GSIO (spi/i2c) present, rev >= 37 */
[all …]
/linux/drivers/soc/ux500/
H A Dux500-soc-id.c53 unsigned int rev = dbx500_id.revision; in ux500_print_soc_info() local
57 if (rev == 0x01) in ux500_print_soc_info()
59 else if (rev >= 0xA0) in ux500_print_soc_info()
60 pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf); in ux500_print_soc_info()
138 unsigned int rev = dbx500_id.revision; in ux500_get_revision() local
140 if (rev == 0x01) in ux500_get_revision()
142 else if (rev >= 0xA0) in ux500_get_revision()
144 (rev >> 4) - 0xA + 1, rev & 0xf); in ux500_get_revision()
/linux/drivers/pinctrl/cirrus/
H A Dpinctrl-lochnagar.c53 #define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \ argument
54 static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = { \
55 .name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \
56 .shift = LOCHNAGAR##REV##_##SHIFT##_SHIFT, .invert = INVERT, \
59 #define LN_PIN_SAIF(REV, ID, NAME) \ argument
60 static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = \
63 #define LN_PIN_AIF(REV, ID) \ argument
64 LN_PIN_SAIF(REV, ID##_BCLK, LN_##ID##_STR"-bclk"); \
65 LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
66 LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_pci.h47 #define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */
48 #define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */
49 #define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */
50 #define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */
67 #define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
68 #define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
69 #define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
70 #define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
85 #define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
86 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
[all …]
H A Dbcma_driver_chipcommon.h50 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
51 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
53 #define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
57 #define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
91 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
92 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
108 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
110 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
132 #define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
133 #define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
[all …]
/linux/arch/x86/kernel/cpu/microcode/
H A Damd.c99 __u32 rev : 8, member
189 static u32 get_cutoff_revision(u32 rev) in get_cutoff_revision() argument
191 switch (rev >> 8) { in get_cutoff_revision()
323 u32 rev, dummy __always_unused; in get_patch_level() local
340 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); in get_patch_level()
342 return rev; in get_patch_level()
723 ucode_dbg("updated rev: 0x%x\n", *cur_rev); in __apply_microcode_amd()
783 u32 rev; in load_ucode_amd_bsp() local
795 rev = get_patch_level(); in load_ucode_amd_bsp()
796 ed->old_rev = rev; in load_ucode_amd_bsp()
[all …]
/linux/include/linux/ssb/
H A Dssb_driver_pci.h50 #define SSB_PCICORE_GPIO_IN 0x0060 /* rev >= 2 only */
51 #define SSB_PCICORE_GPIO_OUT 0x0064 /* rev >= 2 only */
52 #define SSB_PCICORE_GPIO_ENABLE 0x0068 /* rev >= 2 only */
53 #define SSB_PCICORE_GPIO_CTL 0x006C /* rev >= 2 only */
60 #define SSB_PCICORE_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
61 #define SSB_PCICORE_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
62 #define SSB_PCICORE_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
63 #define SSB_PCICORE_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
74 #define SSB_PCICORE_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
H A Dssb_driver_chipcommon.h53 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
54 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
59 #define SSB_CHIPCO_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
88 #define SSB_CHIPCO_CHIPCTL 0x0028 /* Rev >= 11 only */
89 #define SSB_CHIPCO_CHIPSTAT 0x002C /* Rev >= 11 only */
90 #define SSB_CHIPCO_JCMD 0x0030 /* Rev >= 10 only */
112 #define SSB_CHIPCO_JIR 0x0034 /* Rev >= 10 only */
113 #define SSB_CHIPCO_JDR 0x0038 /* Rev >= 10 only */
114 #define SSB_CHIPCO_JCTL 0x003C /* Rev >= 10 only */
125 #define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
[all …]

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