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/linux/include/video/
H A Ds1d13xxxfb.h20 /* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */
25 /* register definitions (tested on s1d13896) */
26 #define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */
27 #define S1DREG_MISC 0x0001 /* Miscellaneous Register */
28 #define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
29 #define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
30 #define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
31 #define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
32 #define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
33 #define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
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/linux/drivers/staging/media/deprecated/atmel/
H A Datmel-isc-regs.h7 /* ISC Control Enable Register 0 */
10 /* ISC Control Disable Register 0 */
13 /* ISC Control Status Register 0 */
21 /* ISC Parallel Front End Configuration 0 Register */
44 /* ISC Parallel Front End Configuration 1 Register */
52 /* ISC Parallel Front End Configuration 2 Register */
60 /* ISC Clock Enable Register */
63 /* ISC Clock Disable Register */
66 /* ISC Clock Status Register */
72 /* ISC Clock Configuration Register */
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/linux/drivers/media/platform/microchip/
H A Dmicrochip-isc-regs.h7 /* ISC Control Enable Register 0 */
10 /* ISC Control Disable Register 0 */
13 /* ISC Control Status Register 0 */
21 /* ISC Parallel Front End Configuration 0 Register */
44 /* ISC Parallel Front End Configuration 1 Register */
52 /* ISC Parallel Front End Configuration 2 Register */
60 /* ISC Clock Enable Register */
63 /* ISC Clock Disable Register */
66 /* ISC Clock Status Register */
72 /* ISC Clock Configuration Register */
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/linux/drivers/pinctrl/
H A Dpinctrl-at91.h12 #define PIO_PER 0x00 /* Enable Register */
13 #define PIO_PDR 0x04 /* Disable Register */
14 #define PIO_PSR 0x08 /* Status Register */
15 #define PIO_OER 0x10 /* Output Enable Register */
16 #define PIO_ODR 0x14 /* Output Disable Register */
17 #define PIO_OSR 0x18 /* Output Status Register */
21 #define PIO_SODR 0x30 /* Set Output Data Register */
22 #define PIO_CODR 0x34 /* Clear Output Data Register */
23 #define PIO_ODSR 0x38 /* Output Data Status Register */
24 #define PIO_PDSR 0x3c /* Pin Data Status Register */
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/linux/arch/arm/mach-sa1100/
H A Djornada720.c56 {0x0001,0x00}, // Miscellaneous Register
57 {0x01FC,0x00}, // Display Mode Register
58 {0x0004,0x00}, // General IO Pins Configuration Register 0
59 {0x0005,0x00}, // General IO Pins Configuration Register 1
60 {0x0008,0x00}, // General IO Pins Control Register 0
61 {0x0009,0x00}, // General IO Pins Control Register 1
62 {0x0010,0x01}, // Memory Clock Configuration Register
63 {0x0014,0x11}, // LCD Pixel Clock Configuration Register
64 {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
65 {0x001C,0x01}, // MediaPlug Clock Configuration Register
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/linux/include/linux/fsl/
H A Dguts.h3 * Freecale 85xx and 86xx Global Utilties register set
21 * you are expected to know whether a given register actually exists on your
29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
32 * Control Register
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
39 * Register
42 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
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/linux/include/soc/fsl/qe/
H A Dimmap_qe.h24 __be32 iadd; /* I-RAM Address Register */
25 __be32 idata; /* I-RAM Data Register */
27 __be32 iready; /* I-RAM Ready Register */
56 __be32 cecr; /* QE command register */
57 __be32 ceccr; /* QE controller configuration register */
58 __be32 cecdr; /* QE command data register */
60 __be16 ceter; /* QE timer event register */
62 __be16 cetmr; /* QE timers mask register */
63 __be32 cetscr; /* QE time-stamp timer control register */
64 __be32 cetsr1; /* QE time-stamp register 1 */
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/linux/include/linux/mfd/
H A Drz-mtu3.h12 /* 8-bit shared register offsets macros */
13 #define RZ_MTU3_TSTRA 0x080 /* Timer start register A */
14 #define RZ_MTU3_TSTRB 0x880 /* Timer start register B */
16 /* 16-bit shared register offset macros */
17 #define RZ_MTU3_TDDRA 0x016 /* Timer dead time data register A */
18 #define RZ_MTU3_TDDRB 0x816 /* Timer dead time data register B */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
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H A Dtps6594.h25 /* Macro to get page index from register address */
248 /* BUCKX_CTRL register field definition */
257 /* TPS6594 BUCKX_CONF register field definition */
261 /* TPS65224 BUCKX_CONF register field definition */
264 /* TPS6594 BUCKX_PG_WINDOW register field definition */
268 /* TPS65224 BUCKX_PG_WINDOW register field definition */
271 /* TPS6594 BUCKX_VOUT register field definition */
274 /* TPS65224 BUCKX_VOUT register field definition */
278 /* LDOX_CTRL register field definition */
286 /* LDORTC_CTRL register field definition */
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H A Dtps65910.h126 * List of register bitfields for component TPS65910
142 /*Register BCK1 (0x80) register.RegisterDescription */
147 /*Register BCK2 (0x80) register.RegisterDescription */
152 /*Register BCK3 (0x80) register.RegisterDescription */
157 /*Register BCK4 (0x80) register.RegisterDescription */
162 /*Register BCK5 (0x80) register.RegisterDescription */
167 /*Register PUADEN (0x80) register.RegisterDescription */
186 /*Register REF (0x80) register.RegisterDescription */
193 /*Register VRTC (0x80) register.RegisterDescription */
200 /*Register VIO (0x80) register.RegisterDescription */
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/linux/arch/arm/mach-pxa/
H A Dpxa27x-udc.h11 #define UDCCR __REG(0x40600000) /* UDC Control Register */
50 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
51 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
59 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
87 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
88 #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
106 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
116 #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
117 #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
118 #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
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/linux/Documentation/devicetree/bindings/cache/
H A Dqcom,llcc.yaml82 - description: LLCC0 base register region
98 - description: LLCC0 base register region
99 - description: LLCC1 base register region
100 - description: LLCC broadcast OR register region
101 - description: LLCC broadcast AND register region
102 - description: LLCC scratchpad broadcast OR register region
103 - description: LLCC scratchpad broadcast AND register region
125 - description: LLCC0 base register region
126 - description: LLCC broadcast base register region
142 - description: LLCC0 base register region
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/linux/include/linux/mfd/da9052/
H A Dreg.h3 * Register declarations for DA9052 PMICs.
23 /* PARK REGISTER */
178 /* STATUS REGISTER A BITS */
188 /* STATUS REGISTER B BITS */
198 /* STATUS REGISTER C BITS */
208 /* STATUS REGISTER D BITS */
218 /* EVENT REGISTER A BITS */
228 /* EVENT REGISTER B BITS */
238 /* EVENT REGISTER C BITS */
248 /* EVENT REGISTER D BITS */
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/linux/arch/powerpc/include/asm/
H A Dmpic_msgr.h23 /* Get a message register
25 * @reg_num: the MPIC message register to get
27 * A pointer to the message register is returned. If
28 * the message register asked for is already in use, then
30 * with an actual message register, then ENODEV is returned.
31 * Successfully getting the register marks it as in use.
35 /* Relinquish a message register
37 * @msgr: the message register to return
39 * Disables the given message register and marks it as free.
41 * register is available to be acquired by a call to
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H A Dmpc5121.h11 u32 rcwlr; /* Reset Configuration Word Low Register */
12 u32 rcwhr; /* Reset Configuration Word High Register */
15 u32 rsr; /* Reset Status Register */
16 u32 rmr; /* Reset Mode Register */
17 u32 rpr; /* Reset Protection Register */
18 u32 rcr; /* Reset Control Register */
19 u32 rcer; /* Reset Control Enable Register */
26 u32 spmr; /* System PLL Mode Register */
27 u32 sccr1; /* System Clock Control Register 1 */
28 u32 sccr2; /* System Clock Control Register 2 */
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H A Dreg_booke.h3 * Contains register definitions common to the Book E PowerPC
14 /* Machine State Register (MSR) Fields */
48 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
49 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
50 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
51 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
52 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
53 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
54 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
55 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
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H A Dipic.h26 #define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
27 #define IPIC_SIVCR 0x04 /* System Global Interrupt Vector Register */
28 #define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */
29 #define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */
30 #define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */
31 #define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */
32 #define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */
33 #define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */
34 #define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */
35 #define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix-i2c-txcommon.h9 /* Register definitions for TX_P2 */
13 * Core Register Definitions
16 /* Device ID Low Byte Register */
19 /* Device ID High Byte Register */
22 /* Device version register */
25 /* Power Down Control Register */
34 /* Reset Control Register 1 */
45 /* Reset Control Register 2 */
51 /* Video Control Register 1 */
58 /* Video Control Register 2 */
[all …]
H A Danalogix-i2c-dptx.h12 /* Register definitions for TX_P0 */
15 /* HDCP Status Register */
20 /* HDCP Control Register 0 */
32 /* HDCP Receiver BSTATUS Register 0 */
34 /* HDCP Receiver BSTATUS Register 1 */
42 /* HDCP Wait R0 Timing Register */
45 /* HDCP Link Integrity Check Timer Register */
48 /* HDCP Repeater Ready Wait Timer Register */
51 /* HDCP Auto Timer Register */
54 /* HDCP Key Status Register */
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/linux/drivers/net/ethernet/sun/
H A Dsungem.h12 #define GREG_SEBSTATE 0x0000UL /* SEB State Register */
13 #define GREG_CFG 0x0004UL /* Configuration Register */
14 #define GREG_STAT 0x000CUL /* Status Register */
15 #define GREG_IMASK 0x0010UL /* Interrupt Mask Register */
16 #define GREG_IACK 0x0014UL /* Interrupt ACK Register */
18 #define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */
19 #define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */
20 #define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */
21 #define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */
22 #define GREG_SWRST 0x1010UL /* Software Reset Register */
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/linux/drivers/scsi/aic7xxx/
H A Daic79xx.reg2 * Aic79xx register and scratch ram definitions.
50 /* Register window Modes */
88 * is added to the register which is referenced in the driver.
89 * Unreferenced register with no dont_generate_debug_code will result
96 * as the source and destination of any register accesses in our
97 * register window.
99 register MODE_PTR {
114 register INTSTAT {
131 register SEQINTCODE {
211 register CLRINT {
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/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h213 /* RCC_SECCFGR register fields */
237 /* RCC_MP_SREQSETR register fields */
240 /* RCC_MP_SREQCLRR register fields */
243 /* RCC_MP_APRSTCR register fields */
248 /* RCC_MP_APRSTSR register fields */
252 /* RCC_PWRLPDLYCR register fields */
256 /* RCC_MP_GRSTCSETR register fields */
260 /* RCC_BR_RSTSCLRR register fields */
272 /* RCC_MP_RSTSSETR register fields */
288 /* RCC_MP_RSTSCLRR register fields */
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/linux/tools/include/nolibc/
H A Darch-sh.h24 register long _num __asm__ ("r3") = (num); \
25 register long _ret __asm__ ("r0"); \
38 register long _num __asm__ ("r3") = (num); \
39 register long _ret __asm__ ("r0"); \
40 register long _arg1 __asm__ ("r4") = (long)(arg1); \
53 register long _num __asm__ ("r3") = (num); \
54 register long _ret __asm__ ("r0"); \
55 register long _arg1 __asm__ ("r4") = (long)(arg1); \
56 register long _arg2 __asm__ ("r5") = (long)(arg2); \
69 register long _num __asm__ ("r3") = (num); \
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H A Darch-mips.h30 * - syscall return comes in v0, and register a3 needs to be checked to know
34 * don't have to experience issues with register constraints.
52 /* binutils, GCC and clang disagree about register aliases, use numbers instead. */
64 register long _num __asm__ ("v0") = (num); \
65 register long _arg4 __asm__ ("a3"); \
80 register long _num __asm__ ("v0") = (num); \
81 register long _arg1 __asm__ ("a0") = (long)(arg1); \
82 register long _arg4 __asm__ ("a3"); \
98 register long _num __asm__ ("v0") = (num); \
99 register long _arg1 __asm__ ("a0") = (long)(arg1); \
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/linux/arch/powerpc/sysdev/
H A Dfsl_pci.h15 /* FSL PCI controller BRR1 register */
40 __be32 potar; /* 0x.0 - Outbound translation address register */
41 __be32 potear; /* 0x.4 - Outbound translation extended address register */
42 __be32 powbar; /* 0x.8 - Outbound window base address register */
44 __be32 powar; /* 0x.10 - Outbound window attributes register */
50 __be32 pitar; /* 0x.0 - Inbound translation address register */
52 __be32 piwbar; /* 0x.8 - Inbound window base address register */
53 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
54 __be32 piwar; /* 0x.10 - Inbound window attributes register */
60 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
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