Searched full:rx_dv (Results 1 – 9 of 9) sorted by relevance
/linux/arch/powerpc/boot/dts/ |
H A D | kmeter1.dts | 161 0 15 2 0 1 0 /* RX_DV */ 187 0 29 2 0 1 0 /* RX_DV */ 208 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ 228 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ 246 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ 264 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ 282 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
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H A D | mpc832x_rdb.dts | 191 0 28 2 0 1 0 /* RX_DV */ 211 1 10 2 0 1 0 /* RX_DV */
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
H A D | pincfg.txt | 50 0 f 2 0 1 0 /* RX_DV */
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/linux/arch/powerpc/boot/dts/fsl/ |
H A D | mpc8568mds.dts | 146 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */ 174 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
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/linux/Documentation/devicetree/bindings/net/ |
H A D | ti,dp83867.yaml | 103 This denotes the fact that the board has RX_DV/RX_CTRL pin strapped in
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/linux/drivers/net/dsa/sja1105/ |
H A D | sja1105_clocking.c | 443 pad_mii_rx.ctrl_ih = 0; /* RX_DV/CRS_DV/RX_CTL and RX_ER */ in sja1105_cfg_pad_rx_config() 446 pad_mii_rx.ctrl_ipud = 3; /* RX_DV/CRS_DV/RX_CTL and RX_ER */ in sja1105_cfg_pad_rx_config() 806 /* Internally pull down the RX_DV/CRS_DV/RX_CTL and RX_ER inputs */ in sja1105_clocking_setup_port()
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/linux/drivers/net/ethernet/atheros/ |
H A D | ag71xx.c | 142 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ 168 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
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/linux/drivers/net/phy/ |
H A D | dp83867.c | 776 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ in dp83867_config_init()
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/linux/drivers/pinctrl/renesas/ |
H A D | pfc-r8a7740.c | 1917 /* RXD[0:3], RX_CLK, RX_DV, RX_ER 1933 /* RXD[0:7], RX_CLK, RX_DV, RX_ER
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