Home
last modified time | relevance | path

Searched full:rs0 (Results 1 – 7 of 7) sorted by relevance

/linux/arch/arm64/kernel/
H A Dsleep.S14 * @rs0: register containing affinity level 0 bit shift
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
32 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3);
34 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
39 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
42 lsr \dst ,\dst, \rs0 // dst=aff0>>rs0
/linux/arch/arm/kernel/
H A Dsleep.S15 * @rs0: register containing affinity level 0 bit shift
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
31 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
33 * Input registers: rs0, rs1, rs2, mpidr, mask
38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
41 ARM( mov \dst, \dst, lsr \rs0 ) @ dst=aff0>>rs0
42 THUMB( lsr \dst, \dst, \rs0 )
/linux/include/linux/rtc/
H A Dds1685.h154 #define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */
291 * Periodic rates are selected by setting the RS3-RS0 bits in Control
295 * E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz
311 /* E32K RS3 RS2 RS1 RS0 */
/linux/drivers/edac/
H A Dpnd2_edac.h223 u32 rs0 : 5; member
/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7724.c285 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
/linux/drivers/net/phy/
H A Dsfp.c1779 seq_printf(s, "rs0: %d\n", !!(sfp->state & SFP_F_RS0)); in sfp_debug_state_show()
2102 * SFF-8079 reveals that it is understood that RS0 will be low for in sfp_module_parse_rate_select()
2138 * Channel 1.0625/2.125/4.25 Gbd modes. Note that RS0 in sfp_module_parse_rate_select()
/linux/drivers/rtc/
H A Drtc-ds1685.c1146 /* Clear RS3-RS0 in Control A. */ in ds1685_rtc_probe()