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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,sdx75-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75
13 RPMh interconnect providers support system bandwidth requirements through
14 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
17 least one RPMh device child node pertaining to their RSC and each provider
18 can map to multiple RPMh resources.
42 - $ref: qcom,rpmh-common.yaml#
67 - description: RPMH CC QPIC Clock
78 #include <dt-bindings/clock/qcom,rpmh.h>
H A Dqcom,qcs615-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,qcs615-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on QCS615
13 RPMh interconnect providers support system bandwidth requirements through
14 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
17 least one RPMh device child node pertaining to their RSC and each provider
18 can map to multiple RPMh resources.
20 See also: include/dt-bindings/interconnect/qcom,qcs615-rpmh.h
42 - description: RPMH CC IPA clock
48 - $ref: qcom,rpmh-common.yaml#
H A Dqcom,qdu1000-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
18 least one RPMh device child node pertaining to their RSC and each provider
19 can map to multiple RPMh resources.
35 - $ref: qcom,rpmh-common.yaml#
57 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
H A Dqcom,milos-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,milos-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on Milos SoC
13 RPMh interconnect providers support system bandwidth requirements through
14 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
17 least one RPMh device child node pertaining to their RSC and each provider
18 can map to multiple RPMh resources.
20 See also: include/dt-bindings/interconnect/qcom,milos-rpmh.h
49 - $ref: qcom,rpmh-common.yaml#
100 - description: RPMH CC IPA clock
H A Dqcom,kaanapali-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,kaanapali-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on Kaanapali
13 RPMh interconnect providers support system bandwidth requirements through
14 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
17 least one RPMh device child node pertaining to their RSC and each provider
18 can map to multiple RPMh resources.
20 See also: include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h
50 - $ref: qcom,rpmh-common.yaml#
90 - description: RPMH CC IPA clock
H A Dqcom,rpmh-common.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,rpmh-common.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
18 least one RPMh device child node pertaining to their RSC and each provider
19 can map to multiple RPMh resources.
32 this interconnect to send RPMh commands.
H A Dqcom,sm8750-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8750-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8750
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
18 least one RPMh device child node pertaining to their RSC and each provider
19 can map to multiple RPMh resources.
21 See also: include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
52 - $ref: qcom,rpmh-common.yaml#
103 - description: RPMH CC IPA clock
H A Dqcom,sm8650-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
18 least one RPMh device child node pertaining to their RSC and each provider
19 can map to multiple RPMh resources.
21 See also: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
52 - $ref: qcom,rpmh-common.yaml#
103 - description: RPMH CC IPA clock
H A Dqcom,sm8550-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
18 least one RPMh device child node pertaining to their RSC and each provider
19 can map to multiple RPMh resources.
21 See also: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
49 - $ref: qcom,rpmh-common.yaml#
100 - description: RPMH CC IPA clock
H A Dqcom,eliza-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,eliza-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on Eliza SoC
13 RPMh interconnect providers support system bandwidth requirements through
14 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
17 least one RPMh device child node pertaining to their RSC and each provider
18 can map to multiple RPMh resources.
20 See also: include/dt-bindings/interconnect/qcom,eliza-rpmh.h
51 - $ref: qcom,rpmh-common.yaml#
89 - description: RPMH CC IPA clock
H A Dqcom,x1e80100-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,x1e80100-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on X1E80100
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
18 least one RPMh device child node pertaining to their RSC and each provider
19 can map to multiple RPMh resources.
21 See also: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
53 - $ref: qcom,rpmh-common.yaml#
H A Dqcom,sar2130p-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sar2130p-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SAR2130P
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
18 least one RPMh device child node pertaining to their RSC and each provider
19 can map to multiple RPMh resources.
21 See also: include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
47 - $ref: qcom,rpmh-common.yaml#
H A Dqcom,sm7150-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm7150-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM7150
13 RPMh interconnect providers support system bandwidth requirements through
14 RPMh hardware accelerators known as Bus Clock Manager (BCM).
16 See also: include/dt-bindings/interconnect/qcom,sm7150-rpmh.h
19 - $ref: qcom,rpmh-common.yaml#
46 - $ref: qcom,rpmh-common.yaml#
H A Dqcom,sm8450-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM).
45 - $ref: qcom,rpmh-common.yaml#
86 - description: RPMH CC IPA clock
107 #include <dt-bindings/clock/qcom,rpmh.h>
H A Dqcom,sm6350-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml#
7 title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect
13 Qualcomm RPMh-based interconnect provider on SM6350.
40 $ref: qcom,rpmh-common.yaml#
58 - $ref: qcom,rpmh-common.yaml#
82 - description: RPMH CC IPA clock
103 #include <dt-bindings/clock/qcom,rpmh.h>
H A Dqcom,qcs8300-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,qcs8300-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on QCS8300
13 RPMh interconnect providers support system bandwidth requirements through
14 RPMh hardware accelerators known as Bus Clock Manager (BCM).
16 See also: include/dt-bindings/interconnect/qcom,qcs8300-rpmh.h
46 - $ref: qcom,rpmh-common.yaml#
86 - description: RPMH CC IPA clock
H A Dqcom,sc7280-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sc7280-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM).
46 - $ref: qcom,rpmh-common.yaml#
83 - description: RPMH CC IPA clock
H A Dqcom,sc8280xp-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sc8280xp-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SC8280XP
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM).
39 - $ref: qcom,rpmh-common.yaml#
H A Dqcom,sa8775p-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sa8775p-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SA8775P
13 RPMh interconnect providers support system bandwidth requirements through
14 RPMh hardware accelerators known as Bus Clock Manager (BCM).
47 - $ref: qcom,rpmh-common.yaml#
75 - description: RPMH CC IPA clock
H A Dqcom,glymur-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur and Mahua SoCs
13 RPMh interconnect providers support system bandwidth requirements through
14 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
17 least one RPMh device child node pertaining to their RSC and each provider
18 can map to multiple RPMh resources.
20 See also: include/dt-bindings/interconnect/qcom,glymur-rpmh.h
128 - $ref: qcom,rpmh-common.yaml#
/linux/drivers/regulator/
H A Dqcom-rpmh-regulator.c19 #include <soc/qcom/rpmh.h>
21 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
24 * enum rpmh_regulator_type - supported RPMh accelerator types
25 * @VRM: RPMh VRM accelerator which supports voting on enable, voltage,
27 * @XOB: RPMh XOB accelerator which supports voting on the enable state
102 * struct rpmh_vreg_hw_data - RPMh regulator hardware configurations
103 * @regulator_type: RPMh accelerator type used to manage this
133 * struct rpmh_vreg - individual RPMh regulator data structure encapsulating a
135 * @dev: Device pointer for the top-level PMIC RPMh
137 * handle in RPMh write requests.
[all …]
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom-stats.yaml22 - qcom,rpmh-stats
23 - qcom,sdm845-rpmh-stats
47 const: qcom,rpmh-stats
55 # Example of rpmh sleep stats
58 compatible = "qcom,rpmh-stats";
/linux/drivers/soc/qcom/
H A Drpmh.c21 #include <soc/qcom/rpmh.h>
23 #include "rpmh-internal.h"
160 * __rpmh_write: Cache and send the RPMH request
166 * Cache the RPMH request and send if the state is ACTIVE_ONLY.
212 * rpmh_write_async: Write a set of RPMH commands
219 * Write a set of RPMH commands, the order of commands is maintained
244 * rpmh_write: Write a set of RPMH commands and block until response
306 * rpmh_write_batch: Write multiple sets of RPMH commands and wait for the
371 pr_err("Error(%d) sending RPMH message addr=%#x\n", in rpmh_write_batch()
459 pr_debug("%s: skipping RPMH req: a:%#x s:%#x w:%#x", in rpmh_flush()
/linux/drivers/interconnect/qcom/
H A Dicc-rpmh.h44 * @unit: divisor used to convert bytes/sec bw value to an RPMh msg
45 * @width: multiplier used to convert bytes/sec bw value to an RPMh msg
114 * @addr: address offsets used when voting to RPMH
122 * communicating with RPMh
H A Dbcm-voter.h10 #include <soc/qcom/rpmh.h>
13 #include "icc-rpmh.h"

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