Home
last modified time | relevance | path

Searched full:reg2 (Results 1 – 25 of 152) sorted by relevance

1234567

/linux/arch/nios2/include/asm/
H A Dasm-macros.h14 * ANDs reg2 with mask and places the result in reg1.
16 * You cannnot use the same register for reg1 & reg2.
19 .macro ANDI32 reg1, reg2, mask
24 and \reg1, \reg1, \reg2
26 andi \reg1, \reg2, %lo(\mask)
29 andhi \reg1, \reg2, %hi(\mask)
34 * ORs reg2 with mask and places the result in reg1.
36 * It is safe to use the same register for reg1 & reg2.
39 .macro ORI32 reg1, reg2, mask
42 orhi \reg1, \reg2, %hi(\mask)
[all …]
/linux/arch/arm/probes/kprobes/
H A Dtest-core.h239 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
240 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
242 TEST_ARG_REG(reg2, val2) \
244 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
247 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
248 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
250 TEST_ARG_REG(reg2, val2) \
253 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
256 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
257 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
[all …]
/linux/arch/arm/lib/
H A Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
48 ldr1w \ptr, \reg2, \abort
53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
66 str1w \ptr, \reg2, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
H A Dcsumpartialcopy.S29 .macro load2b, reg1, reg2 argument
31 ldrb \reg2, [r0], #1
38 .macro load2l, reg1, reg2 argument
40 ldr \reg2, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
H A Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcsumpartialcopyuser.S60 .macro load2b, reg1, reg2 argument
62 ldrusr \reg2, r0, 1
69 .macro load2l, reg1, reg2 argument
71 ldrusr \reg2, r0, 4
74 .macro load4l, reg1, reg2, reg3, reg4
76 ldrusr \reg2, r0, 4
H A Dcopy_template.S27 * ldr4w ptr reg1 reg2 reg3 reg4 abort
28 * ldr8w ptr, reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
41 * str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
47 * enter reg1 reg2
53 * usave reg1 reg2
59 * exit reg1 reg2
/linux/drivers/rtc/
H A Drtc-aspeed.c25 u32 reg1, reg2; in aspeed_rtc_read_time() local
33 reg2 = readl(rtc->base + RTC_YEAR); in aspeed_rtc_read_time()
35 } while (reg2 != readl(rtc->base + RTC_YEAR)); in aspeed_rtc_read_time()
42 cent = (reg2 >> 16) & 0x1f; in aspeed_rtc_read_time()
43 year = (reg2 >> 8) & 0x7f; in aspeed_rtc_read_time()
44 tm->tm_mon = ((reg2 >> 0) & 0x0f) - 1; in aspeed_rtc_read_time()
55 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
64 reg2 = ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) | in aspeed_rtc_set_time()
71 writel(reg2, rtc->base + RTC_YEAR); in aspeed_rtc_set_time()
/linux/arch/parisc/net/
H A Dbpf_jit.h103 #define hppa_or(reg1, reg2, target) \ argument
104 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x09, target) /* or reg1,reg2,target */
105 #define hppa_or_cond(reg1, reg2, cond, f, target) \ argument
106 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x09, target)
107 #define hppa_and(reg1, reg2, target) \ argument
108 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x08, target) /* and reg1,reg2,target */
109 #define hppa_and_cond(reg1, reg2, cond, f, target) \ argument
110 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x08, target)
111 #define hppa_xor(reg1, reg2, target) \ argument
112 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x0a, target) /* xor reg1,reg2,target */
[all …]
/linux/arch/powerpc/kernel/
H A Dkvm_emul.S20 #define LL64(reg, offs, reg2) ld reg, (offs)(reg2) argument
21 #define STL64(reg, offs, reg2) std reg, (offs)(reg2) argument
23 #define LL64(reg, offs, reg2) lwz reg, (offs + 4)(reg2) argument
24 #define STL64(reg, offs, reg2) stw reg, (offs + 4)(reg2) argument
/linux/arch/arm/kernel/
H A Dhyp-stub.S31 .macro store_primary_cpu_mode reg1, reg2 argument
34 str_l \reg1, __boot_cpu_mode, \reg2
43 .macro compare_cpu_mode_with_primary mode, reg1, reg2 argument
44 adr_l \reg2, __boot_cpu_mode
45 ldr \reg1, [\reg2]
48 strne \reg1, [\reg2] @ record what happened and give up
53 .macro store_primary_cpu_mode reg1:req, reg2:req
60 .macro compare_cpu_mode_with_primary mode, reg1, reg2 argument
/linux/drivers/media/dvb-frontends/
H A Dtua6100.c65 u8 reg2[] = { 0x02, 0x00, 0x00 }; in tua6100_set_params() local
68 struct i2c_msg msg2 = { .addr = priv->i2c_address, .flags = 0, .buf = reg2, .len = 3 }; in tua6100_set_params()
92 reg2[1] = (_R_VAL >> 8) & 0x03; in tua6100_set_params()
93 reg2[2] = _R_VAL; in tua6100_set_params()
95 reg2[1] |= 0x1c; in tua6100_set_params()
97 reg2[1] |= 0x0c; in tua6100_set_params()
99 reg2[1] |= 0x1c; in tua6100_set_params()
/linux/drivers/mcb/
H A Dmcb-parse.c43 __le32 reg2; in chameleon_parse_gdd() local
50 reg2 = readl(&gdd->reg2); in chameleon_parse_gdd()
57 mdev->bar = GDD_BAR(reg2); in chameleon_parse_gdd()
58 mdev->group = GDD_GRP(reg2); in chameleon_parse_gdd()
59 mdev->inst = GDD_INS(reg2); in chameleon_parse_gdd()
/linux/sound/pci/ice1712/
H A Dwm8766.c35 .reg2 = WM8766_REG_DACR1,
46 .reg2 = WM8766_REG_DACR2,
57 .reg2 = WM8766_REG_DACR3,
218 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8766_ctl_get()
257 wm->ctl[n].reg1 == wm->ctl[n].reg2) { in snd_wm8766_ctl_put()
264 wm->ctl[n].reg1 != wm->ctl[n].reg2) { in snd_wm8766_ctl_put()
265 val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; in snd_wm8766_ctl_put()
269 snd_wm8766_write(wm, wm->ctl[n].reg2, val); in snd_wm8766_ctl_put()
H A Dwm8776.c134 .reg2 = WM8776_REG_DACRVOL,
144 .reg2 = WM8776_REG_DACCTRL1,
160 .reg2 = WM8776_REG_HPRVOL,
178 .reg2 = WM8776_REG_HPRVOL,
205 .reg2 = WM8776_REG_PHASESWAP,
221 .reg2 = WM8776_REG_ADCRVOL,
231 .reg2 = WM8776_REG_ADCMUX,
488 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8776_ctl_get()
527 wm->ctl[n].reg1 == wm->ctl[n].reg2) { in snd_wm8776_ctl_put()
534 wm->ctl[n].reg1 != wm->ctl[n].reg2) { in snd_wm8776_ctl_put()
[all …]
/linux/arch/s390/kvm/
H A Dintercept.c361 int reg1, reg2, rc; in handle_mvpg_pei() local
363 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_mvpg_pei()
366 rc = guest_translate_address_with_key(vcpu, vcpu->run->s.regs.gprs[reg2], in handle_mvpg_pei()
367 reg2, &srcaddr, GACC_FETCH, 0); in handle_mvpg_pei()
407 int reg1, reg2, cc = 0, r = 0; in handle_sthyi() local
414 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_sthyi()
416 addr = vcpu->run->s.regs.gprs[reg2]; in handle_sthyi()
422 if (reg1 == reg2 || reg1 & 1 || reg2 & 1) in handle_sthyi()
448 r = write_guest(vcpu, addr, reg2, sctns, PAGE_SIZE); in handle_sthyi()
457 vcpu->run->s.regs.gprs[reg2 + 1] = rc; in handle_sthyi()
/linux/drivers/media/tuners/
H A Dtda827x.c241 unsigned char reg2[2]; in tda827xo_set_analog_params() local
279 msg.buf = reg2; in tda827xo_set_analog_params()
281 reg2[0] = 0x80; in tda827xo_set_analog_params()
282 reg2[1] = 0; in tda827xo_set_analog_params()
285 reg2[0] = 0x60; in tda827xo_set_analog_params()
286 reg2[1] = 0xbf; in tda827xo_set_analog_params()
289 reg2[0] = 0x30; in tda827xo_set_analog_params()
290 reg2[1] = tuner_reg[4] + 0x80; in tda827xo_set_analog_params()
294 reg2[0] = 0x30; in tda827xo_set_analog_params()
295 reg2[1] = tuner_reg[4] + 4; in tda827xo_set_analog_params()
[all …]
/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_mdio.c20 u32 reg, reg2; in spl2sw_mdio_access() local
31 reg2 = FIELD_PREP(MAC_CPU_PHY_WT_DATA, wdata) | FIELD_PREP(MAC_CPU_PHY_CMD, cmd) | in spl2sw_mdio_access()
39 writel(reg2, comm->l2sw_reg_base + L2SW_PHY_CNTL_REG0); in spl2sw_mdio_access()
/linux/drivers/devfreq/event/
H A Drockchip-dfi.c743 u32 reg2, reg3; in rk3568_dfi_init() local
745 regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG2, &reg2); in rk3568_dfi_init()
749 dfi->ddr_type = FIELD_GET(RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); in rk3568_dfi_init()
761 dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; in rk3568_dfi_init()
772 u32 reg2, reg3, reg4, reg6; in rk3588_dfi_init() local
774 regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, &reg2); in rk3588_dfi_init()
779 dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); in rk3588_dfi_init()
788 dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; in rk3588_dfi_init()
789 dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2; in rk3588_dfi_init()
792 dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) | in rk3588_dfi_init()
/linux/drivers/net/ethernet/netronome/nfp/bpf/
H A Dverifier.c50 const struct bpf_reg_state *reg2) in nfp_record_adjust_head() argument
59 if (reg2->type != SCALAR_VALUE || !tnum_is_const(reg2->var_off)) in nfp_record_adjust_head()
61 imm = reg2->var_off.value; in nfp_record_adjust_head()
175 const struct bpf_reg_state *reg2 = cur_regs(env) + BPF_REG_2; in nfp_bpf_check_helper_call() local
191 nfp_record_adjust_head(bpf, nfp_prog, meta, reg2); in nfp_bpf_check_helper_call()
204 !nfp_bpf_stack_arg_ok("map_lookup", env, reg2, in nfp_bpf_check_helper_call()
212 !nfp_bpf_stack_arg_ok("map_update", env, reg2, in nfp_bpf_check_helper_call()
222 !nfp_bpf_stack_arg_ok("map_delete", env, reg2, in nfp_bpf_check_helper_call()
305 meta->arg2.reg = *reg2; in nfp_bpf_check_helper_call()
/linux/lib/crc/arm64/
H A Dcrc-t10dif-core.S177 // Fold reg1, reg2 into the next 32 data bytes, storing the result back
178 // into reg1, reg2.
179 .macro fold_32_bytes, p, reg1, reg2 argument
187 pmull16x64_\p fold_consts, \reg2, v9
193 eor \reg2\().16b, \reg2\().16b, v9.16b
195 eor \reg2\().16b, \reg2\().16b, v12.16b
/linux/include/sound/
H A Dsb.h331 #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \ argument
332 ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
353 #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \ argument
356 .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }
/linux/drivers/gpu/ipu-v3/
H A Dipu-dc.c123 u32 reg1, reg2; in dc_write_tmpl() local
127 reg2 = operand >> 12 | opcode << 1 | stop << 9; in dc_write_tmpl()
130 reg2 = operand >> 17 | opcode << 7 | stop << 9; in dc_write_tmpl()
133 reg2 = operand >> 12 | opcode << 4 | stop << 9; in dc_write_tmpl()
136 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4); in dc_write_tmpl()
/linux/lib/crc/arm/
H A Dcrc-t10dif-core.S197 // Fold reg1, reg2 into the next 32 data bytes, storing the result back
198 // into reg1, reg2.
199 .macro fold_32_bytes, reg1, reg2, p
203 pmull16x64_\p FOLD_CONST, \reg2
211 veor.8 \reg2, \reg2, q9

1234567