Home
last modified time | relevance | path

Searched full:reg1 (Results 1 – 25 of 182) sorted by relevance

12345678

/linux/arch/nios2/include/asm/
H A Dasm-macros.h14 * ANDs reg2 with mask and places the result in reg1.
16 * You cannnot use the same register for reg1 & reg2.
19 .macro ANDI32 reg1, reg2, mask
22 movhi \reg1, %hi(\mask)
23 movui \reg1, %lo(\mask)
24 and \reg1, \reg1, \reg2
26 andi \reg1, \reg2, %lo(\mask)
29 andhi \reg1, \reg2, %hi(\mask)
34 * ORs reg2 with mask and places the result in reg1.
36 * It is safe to use the same register for reg1 & reg2.
[all …]
/linux/arch/arm/probes/kprobes/
H A Dtest-core.h239 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
240 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
241 TEST_ARG_REG(reg1, val1) \
244 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
247 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
248 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
249 TEST_ARG_REG(reg1, val1) \
253 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
256 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
257 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
[all …]
/linux/tools/perf/util/annotate-arch/
H A Dannotate-x86.c263 if (!has_reg_type(state, dst->reg1)) in update_insn_state_x86()
266 tsr = &state->regs[dst->reg1]; in update_insn_state_x86()
271 else if (has_reg_type(state, src->reg1) && in update_insn_state_x86()
272 state->regs[src->reg1].kind == TSR_KIND_CONST) in update_insn_state_x86()
273 imm_value = state->regs[src->reg1].imm_value; in update_insn_state_x86()
274 else if (src->reg1 == DWARF_REG_PC) { in update_insn_state_x86()
294 src->reg1 != DWARF_REG_PC && tsr->kind == TSR_KIND_TYPE && !dst->mem_ref)) { in update_insn_state_x86()
297 insn_offset, imm_value, dst->reg1); in update_insn_state_x86()
319 insn_offset, imm_value, dst->reg1); in update_insn_state_x86()
328 if (!has_reg_type(state, dst->reg1)) in update_insn_state_x86()
[all …]
/linux/arch/arm/lib/
H A Dcsumpartialcopy.S25 .macro load1b, reg1 argument
26 ldrb \reg1, [r0], #1
29 .macro load2b, reg1, reg2
30 ldrb \reg1, [r0], #1
34 .macro load1l, reg1 argument
35 ldr \reg1, [r0], #4
38 .macro load2l, reg1, reg2
39 ldr \reg1, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
H A Dcsumpartialcopyuser.S56 .macro load1b, reg1 argument
57 ldrusr \reg1, r0, 1
60 .macro load2b, reg1, reg2
61 ldrusr \reg1, r0, 1
65 .macro load1l, reg1 argument
66 ldrusr \reg1, r0, 4
69 .macro load2l, reg1, reg2
70 ldrusr \reg1, r0, 4
74 .macro load4l, reg1, reg2, reg3, reg4
75 ldrusr \reg1, r0, 4
H A Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
47 ldr1w \ptr, \reg1, \abort
53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
65 str1w \ptr, \reg1, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
H A Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
/linux/sound/pci/ice1712/
H A Dwm8776.c133 .reg1 = WM8776_REG_DACLVOL,
143 .reg1 = WM8776_REG_DACCTRL1,
152 .reg1 = WM8776_REG_DACCTRL1,
159 .reg1 = WM8776_REG_HPLVOL,
170 .reg1 = WM8776_REG_PWRDOWN,
177 .reg1 = WM8776_REG_HPLVOL,
186 .reg1 = WM8776_REG_OUTMUX,
192 .reg1 = WM8776_REG_OUTMUX,
198 .reg1 = WM8776_REG_DACCTRL1,
204 .reg1 = WM8776_REG_PHASESWAP,
[all …]
H A Dwm8766.c34 .reg1 = WM8766_REG_DACL1,
45 .reg1 = WM8766_REG_DACL2,
56 .reg1 = WM8766_REG_DACL3,
66 .reg1 = WM8766_REG_DACCTRL2,
73 .reg1 = WM8766_REG_DACCTRL2,
80 .reg1 = WM8766_REG_DACCTRL2,
87 .reg1 = WM8766_REG_IFCTRL,
93 .reg1 = WM8766_REG_IFCTRL,
99 .reg1 = WM8766_REG_IFCTRL,
105 .reg1 = WM8766_REG_DACCTRL2,
[all …]
/linux/arch/arm/kernel/
H A Dhyp-stub.S31 .macro store_primary_cpu_mode reg1, reg2
32 mrs \reg1, cpsr
33 and \reg1, \reg1, #MODE_MASK
34 str_l \reg1, __boot_cpu_mode, \reg2
43 .macro compare_cpu_mode_with_primary mode, reg1, reg2
45 ldr \reg1, [\reg2]
46 cmp \mode, \reg1 @ matches primary CPU boot mode?
47 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
48 strne \reg1, [\reg2] @ record what happened and give up
53 .macro store_primary_cpu_mode reg1:req, reg2:req
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_pmdemand.c405 u32 reg1, reg2; in intel_pmdemand_init_pmdemand_params() local
418 reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0)); in intel_pmdemand_init_pmdemand_params()
423 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
425 REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
427 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
429 REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
438 REG_FIELD_GET(XE3_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
441 REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
443 REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
520 u32 *reg1, u32 *reg2, bool serialized) in intel_pmdemand_update_params() argument
[all …]
/linux/drivers/rtc/
H A Drtc-aspeed.c25 u32 reg1, reg2; in aspeed_rtc_read_time() local
34 reg1 = readl(rtc->base + RTC_TIME); in aspeed_rtc_read_time()
37 tm->tm_mday = (reg1 >> 24) & 0x1f; in aspeed_rtc_read_time()
38 tm->tm_hour = (reg1 >> 16) & 0x1f; in aspeed_rtc_read_time()
39 tm->tm_min = (reg1 >> 8) & 0x3f; in aspeed_rtc_read_time()
40 tm->tm_sec = (reg1 >> 0) & 0x3f; in aspeed_rtc_read_time()
55 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
61 reg1 = (tm->tm_mday << 24) | (tm->tm_hour << 16) | (tm->tm_min << 8) | in aspeed_rtc_set_time()
70 writel(reg1, rtc->base + RTC_TIME); in aspeed_rtc_set_time()
/linux/arch/parisc/net/
H A Dbpf_jit.h103 #define hppa_or(reg1, reg2, target) \ argument
104 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x09, target) /* or reg1,reg2,target */
105 #define hppa_or_cond(reg1, reg2, cond, f, target) \ argument
106 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x09, target)
107 #define hppa_and(reg1, reg2, target) \ argument
108 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x08, target) /* and reg1,reg2,target */
109 #define hppa_and_cond(reg1, reg2, cond, f, target) \ argument
110 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x08, target)
111 #define hppa_xor(reg1, reg2, target) \ argument
112 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x0a, target) /* xor reg1,reg2,target */
[all …]
/linux/drivers/media/dvb-frontends/
H A Da8293.c29 u8 reg0, reg1; in a8293_set_voltage_slew() local
125 reg1 = 0x82; in a8293_set_voltage_slew()
126 if (reg1 != dev->reg[1]) { in a8293_set_voltage_slew()
127 ret = i2c_master_send(client, &reg1, 1); in a8293_set_voltage_slew()
130 dev->reg[1] = reg1; in a8293_set_voltage_slew()
148 u8 reg0, reg1; in a8293_set_voltage_noslew() local
178 reg1 = 0x82; in a8293_set_voltage_noslew()
179 if (reg1 != dev->reg[1]) { in a8293_set_voltage_noslew()
180 ret = i2c_master_send(client, &reg1, 1); in a8293_set_voltage_noslew()
183 dev->reg[1] = reg1; in a8293_set_voltage_noslew()
H A Dtua6100.c64 u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; in tua6100_set_params() local
67 struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 }; in tua6100_set_params()
82 reg1[1] = 0x2c; in tua6100_set_params()
84 reg1[1] = 0x0c; in tua6100_set_params()
87 reg1[1] |= 0x40; in tua6100_set_params()
89 reg1[1] |= 0x80; in tua6100_set_params()
107 reg1[1] |= (div >> 9) & 0x03; in tua6100_set_params()
108 reg1[2] = div >> 1; in tua6100_set_params()
109 reg1[3] = (div << 7); in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
/linux/arch/s390/kvm/
H A Dtrace.h287 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
288 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
293 __field(int, reg1)
301 __entry->reg1 = reg1;
308 __entry->reg1, __entry->reg3, __entry->addr)
312 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
313 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
318 __field(int, reg1)
326 __entry->reg1 = reg1;
333 __entry->reg1, __entry->reg3, __entry->addr)
/linux/drivers/mcb/
H A Dmcb-parse.c42 __le32 reg1; in chameleon_parse_gdd() local
49 reg1 = readl(&gdd->reg1); in chameleon_parse_gdd()
54 mdev->id = GDD_DEV(reg1); in chameleon_parse_gdd()
55 mdev->rev = GDD_REV(reg1); in chameleon_parse_gdd()
56 mdev->var = GDD_VAR(reg1); in chameleon_parse_gdd()
88 mdev->irq.start = GDD_IRQ(reg1); in chameleon_parse_gdd()
89 mdev->irq.end = GDD_IRQ(reg1); in chameleon_parse_gdd()
115 /* skip reg1 */ in chameleon_parse_bar()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c178 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
179 .enable_reg = SRI(reg1, block, reg_num),\
180 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
182 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
183 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
196 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
197 .enable_reg = SRI_DMUB(reg1),\
199 reg1 ## __ ## mask1 ## _MASK,\
201 reg1 ## __ ## mask1 ## _MASK,\
202 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn36/
H A Dirq_service_dcn36.c158 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
159 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
161 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
163 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
165 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
172 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
173 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
175 reg1 ## __ ## mask1 ## _MASK,\
177 reg1 ## __ ## mask1 ## _MASK,\
179 ~reg1 ## __ ## mask1 ## _MASK, \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c159 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
160 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
162 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
164 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
166 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
173 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
174 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
176 reg1 ## __ ## mask1 ## _MASK,\
178 reg1 ## __ ## mask1 ## _MASK,\
180 ~reg1 ## __ ## mask1 ## _MASK, \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/
H A Dirq_service_dcn401.c172 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
173 .enable_reg = SRI(reg1, block, reg_num),\
175 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
177 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
178 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
186 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
187 .enable_reg = SRI_DMUB(reg1),\
189 reg1 ## __ ## mask1 ## _MASK,\
191 reg1 ## __ ## mask1 ## _MASK,\
192 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
187 .enable_reg = SRI(reg1, block, reg_num),\
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
200 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
201 .enable_reg = SRI_DMUB(reg1),\
203 reg1 ## __ ## mask1 ## _MASK,\
205 reg1 ## __ ## mask1 ## _MASK,\
206 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
194 .enable_reg = SRI(reg1, block, reg_num),\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
207 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
208 .enable_reg = SRI_DMUB(reg1),\
210 reg1 ## __ ## mask1 ## _MASK,\
212 reg1 ## __ ## mask1 ## _MASK,\
213 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
189 .enable_reg = SRI(reg1, block, reg_num),\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
202 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
203 .enable_reg = SRI_DMUB(reg1),\
205 reg1 ## __ ## mask1 ## _MASK,\
207 reg1 ## __ ## mask1 ## _MASK,\
208 ~reg1 ## __ ## mask1 ## _MASK \

12345678