| /linux/Documentation/gpu/amdgpu/ |
| H A D | ras.rst | 2 AMDGPU RAS Support
5 The AMDGPU RAS interfaces are exposed via sysfs (for informational queries) and
8 RAS debugfs/sysfs Control and Error Injection Interfaces
12 :doc: AMDGPU RAS debugfs control interface
14 RAS Reboot Behavior for Unrecoverable Errors
18 :doc: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
20 RAS Error Count sysfs Interface
24 :doc: AMDGPU RAS sysfs Error Count Interface
26 RAS EEPROM debugfs Interface
30 :doc: AMDGPU RAS debugfs EEPROM table reset interface
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_mmhub.c | 27 struct amdgpu_mmhub_ras *ras; in amdgpu_mmhub_ras_sw_init() local
29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
35 dev_err(adev->dev, "Failed to register mmhub ras block!\n"); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
44 /* mmhub ras follows amdgpu_ras_block_late_init_default for late init */ in amdgpu_mmhub_ras_sw_init()
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| H A D | amdgpu_mca.c | 33 if (adev->umc.ras->check_ecc_err_status) in amdgpu_mca_is_deferred_error()
34 return adev->umc.ras->check_ecc_err_status(adev, in amdgpu_mca_is_deferred_error()
87 struct amdgpu_mca_ras_block *ras; in amdgpu_mca_mp0_ras_sw_init() local
89 if (!adev->mca.mp0.ras) in amdgpu_mca_mp0_ras_sw_init()
92 ras = adev->mca.mp0.ras; in amdgpu_mca_mp0_ras_sw_init()
94 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp0_ras_sw_init()
96 dev_err(adev->dev, "Failed to register mca.mp0 ras block!\n"); in amdgpu_mca_mp0_ras_sw_init()
100 strcpy(ras->ras_block.ras_comm.name, "mca.mp0"); in amdgpu_mca_mp0_ras_sw_init()
101 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp0_ras_sw_init()
102 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mca_mp0_ras_sw_init()
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| H A D | amdgpu_nbio.c | 28 struct amdgpu_nbio_ras *ras; in amdgpu_nbio_ras_sw_init() local
30 if (!adev->nbio.ras) in amdgpu_nbio_ras_sw_init()
33 ras = adev->nbio.ras; in amdgpu_nbio_ras_sw_init()
34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_nbio_ras_sw_init()
36 dev_err(adev->dev, "Failed to register pcie_bif ras block!\n"); in amdgpu_nbio_ras_sw_init()
40 strcpy(ras->ras_block.ras_comm.name, "pcie_bif"); in amdgpu_nbio_ras_sw_init()
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF; in amdgpu_nbio_ras_sw_init()
42 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
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| H A D | amdgpu_sdma.c | 314 struct amdgpu_sdma_ras *ras = NULL; in amdgpu_sdma_ras_sw_init() local
316 /* adev->sdma.ras is NULL, which means sdma does not in amdgpu_sdma_ras_sw_init()
317 * support ras function, then do nothing here. in amdgpu_sdma_ras_sw_init()
319 if (!adev->sdma.ras) in amdgpu_sdma_ras_sw_init()
322 ras = adev->sdma.ras; in amdgpu_sdma_ras_sw_init()
324 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_sdma_ras_sw_init()
326 dev_err(adev->dev, "Failed to register sdma ras block!\n"); in amdgpu_sdma_ras_sw_init()
330 strcpy(ras->ras_block.ras_comm.name, "sdma"); in amdgpu_sdma_ras_sw_init()
331 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in amdgpu_sdma_ras_sw_init()
332 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_sdma_ras_sw_init()
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| H A D | amdgpu_jpeg.c | 317 struct amdgpu_jpeg_ras *ras; in amdgpu_jpeg_ras_sw_init() local
319 if (!adev->jpeg.ras) in amdgpu_jpeg_ras_sw_init()
322 ras = adev->jpeg.ras; in amdgpu_jpeg_ras_sw_init()
323 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_jpeg_ras_sw_init()
325 dev_err(adev->dev, "Failed to register jpeg ras block!\n"); in amdgpu_jpeg_ras_sw_init()
329 strcpy(ras->ras_block.ras_comm.name, "jpeg"); in amdgpu_jpeg_ras_sw_init()
330 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in amdgpu_jpeg_ras_sw_init()
331 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_jpeg_ras_sw_init()
332 adev->jpeg.ras_if = &ras->ras_block.ras_comm; in amdgpu_jpeg_ras_sw_init()
334 if (!ras->ras_block.ras_late_init) in amdgpu_jpeg_ras_sw_init()
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| H A D | umc_v6_7.c | 101 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_correctable_error_count() local
109 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_correctable_error_count()
116 if (ras->umc_ecc.record_ce_addr_supported) { in umc_v6_7_ecc_info_query_correctable_error_count()
121 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr; in umc_v6_7_ecc_info_query_correctable_error_count()
143 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_querry_uncorrectable_error_count() local
150 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
228 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_error_address() local
232 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_error_address()
244 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v6_7_ecc_info_query_error_address()
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| H A D | umc_v8_7.c | 56 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_correctable_error_count() local
63 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_correctable_error_count()
75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_querry_uncorrectable_error_count() local
80 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_error_address() local
140 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_error_address()
152 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_7_ecc_info_query_error_address()
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| H A D | umc_v8_10.c | 341 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_correctable_error_count() local
349 ecc_ce_cnt = ras->umc_ecc.ecc[eccinfo_table_idx].ce_count_lo_chip; in umc_v8_10_ecc_info_query_correctable_error_count()
360 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_uncorrectable_error_count() local
368 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_uncorrectable_error_count()
408 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_error_address() local
415 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_error_address()
428 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_10_ecc_info_query_error_address()
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| H A D | gfx_v11_0_3.c | 60 dev_err(adev->dev, "Gfx or sdma ras block not initialized, rlc_status0:0x%x.\n", in gfx_v11_0_3_rlc_gc_fed_irq()
95 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in gfx_v11_0_3_poison_consumption_handler() local
97 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET; in gfx_v11_0_3_poison_consumption_handler()
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| H A D | amdgpu_gfx.c | 1014 struct amdgpu_gfx_ras *ras = NULL; in amdgpu_gfx_ras_sw_init() local
1016 /* adev->gfx.ras is NULL, which means gfx does not in amdgpu_gfx_ras_sw_init()
1017 * support ras function, then do nothing here. in amdgpu_gfx_ras_sw_init()
1019 if (!adev->gfx.ras) in amdgpu_gfx_ras_sw_init()
1022 ras = adev->gfx.ras; in amdgpu_gfx_ras_sw_init()
1024 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_gfx_ras_sw_init()
1026 dev_err(adev->dev, "Failed to register gfx ras block!\n"); in amdgpu_gfx_ras_sw_init()
1030 strcpy(ras->ras_block.ras_comm.name, "gfx"); in amdgpu_gfx_ras_sw_init()
1031 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; in amdgpu_gfx_ras_sw_init()
1032 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_gfx_ras_sw_init()
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| H A D | sdma_v4_4.c | 222 * SDMA RAS supports single bit uncorrectable error detection. in sdma_v4_4_query_ras_error_count_by_instance()
228 * SDMA RAS does not support correctable errors. in sdma_v4_4_query_ras_error_count_by_instance()
258 dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i); in sdma_v4_4_query_ras_error_count()
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| H A D | amdgpu_vcn.c | 1322 struct amdgpu_vcn_ras *ras; in amdgpu_vcn_ras_sw_init() local
1324 if (!adev->vcn.ras) in amdgpu_vcn_ras_sw_init()
1327 ras = adev->vcn.ras; in amdgpu_vcn_ras_sw_init()
1328 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_vcn_ras_sw_init()
1330 dev_err(adev->dev, "Failed to register vcn ras block!\n"); in amdgpu_vcn_ras_sw_init()
1334 strcpy(ras->ras_block.ras_comm.name, "vcn"); in amdgpu_vcn_ras_sw_init()
1335 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; in amdgpu_vcn_ras_sw_init()
1336 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_vcn_ras_sw_init()
1337 adev->vcn.ras_if = &ras->ras_block.ras_comm; in amdgpu_vcn_ras_sw_init()
1339 if (!ras->ras_block.ras_late_init) in amdgpu_vcn_ras_sw_init()
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| /linux/drivers/ras/ |
| H A D | Kconfig | 2 menuconfig RAS config
3 bool "Reliability, Availability and Serviceability (RAS) features"
5 Reliability, availability and serviceability (RAS) is a computer
7 of RAS have a multitude of features that protect data integrity
32 if RAS
34 source "arch/x86/ras/Kconfig"
35 source "drivers/ras/amd/atl/Kconfig"
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| H A D | debugfs.c | 3 #include <linux/ras.h>
64 ras_debugfs_dir = debugfs_create_dir("ras", NULL); in ras_debugfs_init()
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| /linux/drivers/accel/qaic/ |
| H A D | qaic_ras.c | 70 /* RAS version number */
73 /* RAS message type */
76 /* Size of RAS message without the header in byte */
92 * Stores the error type, there are three types of error in RAS
294 pci_warn(qdev->pdev, "Dropping RAS message with invalid magic %x\n", msg->magic); in decode_ras_msg()
299 pci_warn(qdev->pdev, "Dropping RAS message with invalid version %d\n", msg->ver); in decode_ras_msg()
304 pci_warn(qdev->pdev, "Dropping non-PUSH RAS message\n"); in decode_ras_msg()
309 pci_warn(qdev->pdev, "Dropping RAS message with invalid len %d\n", msg->len); in decode_ras_msg()
314 pci_warn(qdev->pdev, "Dropping RAS message with err type %d\n", msg->err_type); in decode_ras_msg()
325 …dev_printk(level, &qdev->pdev->dev, "RAS event.\nClass:%s\nDescription:%s %s %s\nError Threshold f… in decode_ras_msg()
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| /linux/net/netfilter/ |
| H A D | nf_conntrack_h323_main.c | 1299 /* Avoid RAS expectation loops. A GCF is never expected. */ in process_gcf()
1312 pr_debug("nf_ct_ras: expect RAS "); in process_gcf()
1387 pr_debug("nf_ct_ras: set RAS connection timeout to " in process_rcf()
1626 unsigned char **data, RasMessage *ras) in process_ras() argument
1628 switch (ras->choice) { in process_ras()
1631 &ras->gatekeeperRequest); in process_ras()
1634 &ras->gatekeeperConfirm); in process_ras()
1637 &ras->registrationRequest); in process_ras()
1640 &ras->registrationConfirm); in process_ras()
1643 &ras->unregistrationRequest); in process_ras()
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| /linux/drivers/gpu/drm/amd/ras/rascore/ |
| H A D | ras_log_ring.c | 24 #include "ras.h"
52 "Error: the logged ras count should not less than 0!\n"); in ras_log_ring_get_logged_ecc_count()
60 "Error: the logged ras count is out of range!\n"); in ras_log_ring_get_logged_ecc_count()
95 "Failed to add ras log! seqno:0x%llx, ret:%d\n", in ras_log_ring_add_data()
243 RAS_DEV_ERR(ras_core->dev, "ERROR: Failed to alloc ras log buffer!\n"); in ras_log_ring_add_log_event()
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| /linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
| H A D | hclge_err.c | 2197 * @is_ras: true for ras, false for msix
2241 /* hclge_handle_mpf_ras_error: handle all main PF RAS errors
2246 * This function handles all the main PF RAS errors in the
2259 /* query all main PF RAS errors */ in hclge_handle_mpf_ras_error()
2264 dev_err(dev, "query all mpf ras int cmd failed (%d)\n", ret); in hclge_handle_mpf_ras_error()
2390 /* clear all main PF RAS errors */ in hclge_handle_mpf_ras_error()
2394 dev_err(dev, "clear all mpf ras int cmd failed (%d)\n", ret); in hclge_handle_mpf_ras_error()
2399 /* hclge_handle_pf_ras_error: handle all PF RAS errors
2404 * This function handles all the PF RAS errors in the
2417 /* query all PF RAS errors */ in hclge_handle_pf_ras_error()
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| /linux/drivers/misc/ |
| H A D | smpro-errmon.c | 14 /* GPI RAS Error Registers */
33 /* RAS Error/Warning Registers */
95 u8 count; /* Number of the RAS errors */
158 * one type of RAS Internal errors.
294 * Reference to section 5.10 RAS Internal Error Register Definition in
357 * Reference to section 5.10 RAS Internal Error Register Definition in
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| /linux/drivers/tty/ipwireless/ |
| H A D | network.c | 327 * If it's associated with a tty (other than the RAS channel in ipwireless_network_notify_control_line_change()
328 * when we're online), then send the data to that tty. The RAS in ipwireless_network_notify_control_line_change()
379 * If it's associated with a tty (other than the RAS channel in ipwireless_network_packet_received()
380 * when we're online), then send the data to that tty. The RAS in ipwireless_network_packet_received()
389 * If data came in on the RAS channel and this tty is in ipwireless_network_packet_received()
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| /linux/Documentation/edac/ |
| H A D | scrub.rst | 143 which provides interfaces for platform RAS features and supports independent
144 RAS controls and capabilities for a given RAS feature for multiple instances
147 Memory RAS features apply to RAS capabilities, controls and operations that
148 are specific to memory. RAS2 PCC sub-spaces for memory-specific RAS features
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| /linux/drivers/edac/ |
| H A D | i5100_edac.c | 433 unsigned ras, in i5100_handle_ce() argument
440 "bank %u, cas %u, ras %u\n", in i5100_handle_ce()
441 bank, cas, ras); in i5100_handle_ce()
455 unsigned ras, in i5100_handle_ue() argument
462 "bank %u, cas %u, ras %u\n", in i5100_handle_ue()
463 bank, cas, ras); in i5100_handle_ue()
483 unsigned ras; in i5100_read_log() local
503 ras = i5100_recmemb_ras(dw2); in i5100_read_log()
512 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
525 ras = i5100_nrecmemb_ras(dw2); in i5100_read_log()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega20_baco.c | 75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
86 if (!ras || !adev->ras_enabled) { in vega20_baco_set_state()
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| /linux/Documentation/arch/arm64/ |
| H A D | acpi_object_usage.rst | 35 compliant with the Arm RAS architecture.
55 Must be supplied if RAS support is provided by the platform. It
150 On a platform supports RAS, this table must be supplied if it is not
212 Must be supplied if RAS support is provided by the platform. It
356 **RAS Features 2 table**
358 This table provides interfaces for the RAS capabilities implemented in
363 **RAS Feature table**
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