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/linux/Documentation/gpu/amdgpu/
H A Dras.rst2 AMDGPU RAS Support
5 The AMDGPU RAS interfaces are exposed via sysfs (for informational queries) and
8 RAS debugfs/sysfs Control and Error Injection Interfaces
12 :doc: AMDGPU RAS debugfs control interface
14 RAS Reboot Behavior for Unrecoverable Errors
18 :doc: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
20 RAS Error Count sysfs Interface
24 :doc: AMDGPU RAS sysfs Error Count Interface
26 RAS EEPROM debugfs Interface
30 :doc: AMDGPU RAS debugfs EEPROM table reset interface
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umc.c123 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
124 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_handle_bad_pages()
125 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, in amdgpu_umc_handle_bad_pages()
128 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
129 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_handle_bad_pages()
148 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, in amdgpu_umc_handle_bad_pages()
153 if (adev->umc.ras && in amdgpu_umc_handle_bad_pages()
154 adev->umc.ras->ecc_info_query_ras_error_count) in amdgpu_umc_handle_bad_pages()
155 adev->umc.ras->ecc_info_query_ras_error_count(adev, in amdgpu_umc_handle_bad_pages()
158 if (adev->umc.ras && in amdgpu_umc_handle_bad_pages()
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H A Damdgpu_mmhub.c27 struct amdgpu_mmhub_ras *ras; in amdgpu_mmhub_ras_sw_init() local
29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
35 dev_err(adev->dev, "Failed to register mmhub ras block!\n"); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
44 /* mmhub ras follows amdgpu_ras_block_late_init_default for late init */ in amdgpu_mmhub_ras_sw_init()
H A Damdgpu_ras_eeprom.c56 * The RAS table lives either at address 0 or address 40000h of EEPROM.
107 * | EEPROM TABLE RAS INFO |
127 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM
335 "Failed to alloc buf to write table ras info\n"); in __write_table_ras_info()
350 dev_err(adev->dev, "Failed to write EEPROM table ras info:%d", in __write_table_ras_info()
441 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
444 * Reset the contents of the header of the RAS EEPROM table.
591 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", in amdgpu_ras_eeprom_check_err_threshold()
771 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_eeprom_update_header() local
779 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
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H A Damdgpu_virt.c54 "RAS TELEMETRY",
251 * amdgpu_virt_rcvd_ras_interrupt() - receive ras interrupt
253 * Check whether host sent RAS error message
294 * @data: VF RAS error-handler data
325 "RAS WARN: failed to grow bad page table to %u slots\n", in amdgpu_virt_ras_realloc_eh_data_space()
430 "RAS WARN: bad page table at capacity (count=%d pages=%d max=%u)\n", in amdgpu_virt_ras_add_bps()
464 * 1) a ras bad page has been allocated (used by someone); in amdgpu_virt_ras_reserve_bps()
465 * 2) a ras bad page has been reserved (duplicate error injection in amdgpu_virt_ras_reserve_bps()
478 "RAS WARN: reserve vram for retired page %llx fail\n", in amdgpu_virt_ras_reserve_bps()
988 ratelimit_state_init(&adev->virt.ras.ras_error_cnt_rs, 5 * HZ, 1); in amdgpu_virt_init_ras()
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H A Dumc_v6_7.c101 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_correctable_error_count() local
109 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_correctable_error_count()
116 if (ras->umc_ecc.record_ce_addr_supported) { in umc_v6_7_ecc_info_query_correctable_error_count()
121 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr; in umc_v6_7_ecc_info_query_correctable_error_count()
143 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_querry_uncorrectable_error_count() local
150 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
228 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_error_address() local
232 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_error_address()
244 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v6_7_ecc_info_query_error_address()
H A Dumc_v8_7.c56 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_correctable_error_count() local
63 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_correctable_error_count()
75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_querry_uncorrectable_error_count() local
80 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_error_address() local
140 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_error_address()
152 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_7_ecc_info_query_error_address()
H A Dumc_v8_10.c341 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_correctable_error_count() local
349 ecc_ce_cnt = ras->umc_ecc.ecc[eccinfo_table_idx].ce_count_lo_chip; in umc_v8_10_ecc_info_query_correctable_error_count()
360 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_uncorrectable_error_count() local
368 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_uncorrectable_error_count()
408 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_error_address() local
415 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_error_address()
428 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_10_ecc_info_query_error_address()
H A Dgfx_v11_0_3.c60 dev_err(adev->dev, "Gfx or sdma ras block not initialized, rlc_status0:0x%x.\n", in gfx_v11_0_3_rlc_gc_fed_irq()
95 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in gfx_v11_0_3_poison_consumption_handler() local
97 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET; in gfx_v11_0_3_poison_consumption_handler()
H A Damdgpu_gfx.c1119 struct amdgpu_gfx_ras *ras = NULL; in amdgpu_gfx_ras_sw_init() local
1121 /* adev->gfx.ras is NULL, which means gfx does not in amdgpu_gfx_ras_sw_init()
1122 * support ras function, then do nothing here. in amdgpu_gfx_ras_sw_init()
1124 if (!adev->gfx.ras) in amdgpu_gfx_ras_sw_init()
1127 ras = adev->gfx.ras; in amdgpu_gfx_ras_sw_init()
1129 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_gfx_ras_sw_init()
1131 dev_err(adev->dev, "Failed to register gfx ras block!\n"); in amdgpu_gfx_ras_sw_init()
1135 strcpy(ras->ras_block.ras_comm.name, "gfx"); in amdgpu_gfx_ras_sw_init()
1136 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; in amdgpu_gfx_ras_sw_init()
1137 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_gfx_ras_sw_init()
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H A Dnbio_v7_9.c523 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in nbio_v7_9_handle_ras_controller_intr_no_bifring() local
538 if (ras && !ras->disable_ras_err_cnt_harvest && obj) { in nbio_v7_9_handle_ras_controller_intr_no_bifring()
563 dev_info(adev->dev, "RAS controller interrupt triggered " in nbio_v7_9_handle_ras_controller_intr_no_bifring()
652 /* register ras controller interrupt */ in nbio_v7_9_init_ras_controller_interrupt()
670 /* register ras err event athub interrupt */ in nbio_v7_9_init_ras_err_event_athub_interrupt()
H A Damdgpu_xgmi.c1332 struct amdgpu_xgmi_ras *ras; in amdgpu_xgmi_ras_sw_init() local
1334 if (!adev->gmc.xgmi.ras) in amdgpu_xgmi_ras_sw_init()
1337 ras = adev->gmc.xgmi.ras; in amdgpu_xgmi_ras_sw_init()
1338 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_xgmi_ras_sw_init()
1340 dev_err(adev->dev, "Failed to register xgmi_wafl_pcs ras block!\n"); in amdgpu_xgmi_ras_sw_init()
1344 strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl"); in amdgpu_xgmi_ras_sw_init()
1345 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL; in amdgpu_xgmi_ras_sw_init()
1346 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_xgmi_ras_sw_init()
1347 adev->gmc.xgmi.ras_if = &ras->ras_block.ras_comm; in amdgpu_xgmi_ras_sw_init()
1393 * switch) the RAS IP block hw_init was skipped under the in amdgpu_xgmi_reset_on_init_work()
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H A Dsdma_v4_4.c222 * SDMA RAS supports single bit uncorrectable error detection. in sdma_v4_4_query_ras_error_count_by_instance()
228 * SDMA RAS does not support correctable errors. in sdma_v4_4_query_ras_error_count_by_instance()
258 dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i); in sdma_v4_4_query_ras_error_count()
/linux/drivers/cxl/core/
H A Dras.c147 if (!map->component_map.ras.valid) in cxl_dport_map_ras()
148 dev_dbg(dev, "RAS registers not found\n"); in cxl_dport_map_ras()
151 dev_dbg(dev, "Failed to map RAS capability.\n"); in cxl_dport_map_ras()
155 * devm_cxl_dport_ras_setup - Setup CXL RAS report on this dport
186 if (!map->component_map.ras.valid) { in devm_cxl_port_ras_setup()
187 dev_dbg(&port->dev, "RAS registers not found\n"); in devm_cxl_port_ras_setup()
194 dev_dbg(&port->dev, "Failed to map RAS capability\n"); in devm_cxl_port_ras_setup()
232 * Log the state of the RAS status registers and prepare them to log the
285 cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras); in cxl_cor_error_detected()
311 * chance the situation is recoverable dump the status of the RAS in cxl_error_detected()
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/linux/include/cxl/
H A Dcxl.h36 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure
40 void __iomem *ras;
57 * RCH downstream port specific RAS register
82 struct cxl_reg_map ras; member
161 * @reg_map: component and ras register mapping parameters
/linux/net/netfilter/
H A Dnf_conntrack_h323_main.c1284 /* Avoid RAS expectation loops. A GCF is never expected. */ in process_gcf()
1297 pr_debug("nf_ct_ras: expect RAS "); in process_gcf()
1378 pr_debug("nf_ct_ras: set RAS connection timeout to " in process_rcf()
1623 unsigned char **data, RasMessage *ras) in process_ras() argument
1625 switch (ras->choice) { in process_ras()
1628 &ras->gatekeeperRequest); in process_ras()
1631 &ras->gatekeeperConfirm); in process_ras()
1634 &ras->registrationRequest); in process_ras()
1637 &ras->registrationConfirm); in process_ras()
1640 &ras->unregistrationRequest); in process_ras()
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/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_err.c2198 * @is_ras: true for ras, false for msix
2242 /* hclge_handle_mpf_ras_error: handle all main PF RAS errors
2247 * This function handles all the main PF RAS errors in the
2260 /* query all main PF RAS errors */ in hclge_handle_mpf_ras_error()
2265 dev_err(dev, "query all mpf ras int cmd failed (%d)\n", ret); in hclge_handle_mpf_ras_error()
2391 /* clear all main PF RAS errors */ in hclge_handle_mpf_ras_error()
2395 dev_err(dev, "clear all mpf ras int cmd failed (%d)\n", ret); in hclge_handle_mpf_ras_error()
2400 /* hclge_handle_pf_ras_error: handle all PF RAS errors
2405 * This function handles all the PF RAS errors in the
2418 /* query all PF RAS errors */ in hclge_handle_pf_ras_error()
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/linux/include/uapi/drm/
H A Damdgpu_drm.h270 /* indicate some errors are detected by RAS */
1235 /* query ras mask of enabled features*/
1237 /* RAS MASK: UMC (VRAM) */
1239 /* RAS MASK: SDMA */
1241 /* RAS MASK: GFX */
1243 /* RAS MASK: MMHUB */
1245 /* RAS MASK: ATHUB */
1247 /* RAS MASK: PCIE */
1249 /* RAS MASK: HDP */
1251 /* RAS MASK: XGMI */
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/linux/drivers/ras/
H A Ddebugfs.c3 #include <linux/ras.h>
64 ras_debugfs_dir = debugfs_create_dir("ras", NULL); in ras_debugfs_init()
/linux/drivers/misc/
H A Dsmpro-errmon.c13 /* GPI RAS Error Registers */
32 /* RAS Error/Warning Registers */
94 u8 count; /* Number of the RAS errors */
157 * one type of RAS Internal errors.
293 * Reference to section 5.10 RAS Internal Error Register Definition in
356 * Reference to section 5.10 RAS Internal Error Register Definition in
/linux/Documentation/edac/
H A Dscrub.rst143 which provides interfaces for platform RAS features and supports independent
144 RAS controls and capabilities for a given RAS feature for multiple instances
147 Memory RAS features apply to RAS capabilities, controls and operations that
148 are specific to memory. RAS2 PCC sub-spaces for memory-specific RAS features
/linux/include/trace/events/
H A Dmemory-failure.h4 * For historical versions, memory_failure_event is in ras subsystem,
7 #define TRACE_SYSTEM ras
/linux/include/drm/
H A Ddrm_ras.h14 * struct drm_ras_node - A DRM RAS Node
41 * This callback is used by drm-ras to query a specific error counter.
/linux/drivers/net/ethernet/sfc/
H A Defx_cxl.c61 if (!cxl->cxlds.reg_map.component_map.ras.valid) { in efx_cxl_init()
62 pci_err(pci_dev, "Expected RAS component register not found\n"); in efx_cxl_init()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_baco.c75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
86 if (!ras || !adev->ras_enabled) { in vega20_baco_set_state()

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