| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | memory.json | 8 …ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (includ…
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | memory.json | 8 …ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (includ…
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | memory.json | 8 "PublicDescription": "Counts any detected correctable or uncorrectable physical memory errors (ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (including data and tag rams). Any detected memory error (from either a speculative and abandoned access, or an architecturally executed access) is counted. Note that errors are only detected when the actual protected memory is accessed by an operation."
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| /linux/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| H A D | memory.json | 21 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| H A D | exception.json | 6 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
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| /linux/arch/xtensa/variants/fsf/include/variant/ |
| H A D | core.h | 165 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
167 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
168 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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| /linux/kernel/ |
| H A D | resource.c | 454 struct resource res, *rams; in walk_system_ram_res_rev() local
460 rams = kvcalloc(rams_size, sizeof(struct resource), GFP_KERNEL); in walk_system_ram_res_rev()
461 if (!rams) in walk_system_ram_res_rev()
472 rams_new = kvrealloc(rams, (rams_size + 16) * sizeof(struct resource), in walk_system_ram_res_rev()
477 rams = rams_new; in walk_system_ram_res_rev()
481 rams[i++] = res; in walk_system_ram_res_rev()
487 ret = (*func)(&rams[i], arg); in walk_system_ram_res_rev()
493 kvfree(rams); in walk_system_ram_res_rev()
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| /linux/arch/arc/ |
| H A D | Kconfig | 242 Single Cycle RAMS to store Fast Path Code
252 Single Cycle RAMS to store Fast Path Data
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| /linux/arch/xtensa/variants/dc232b/include/variant/ |
| H A D | core.h | 172 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
174 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
175 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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| /linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/ |
| H A D | core.h | 185 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
187 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
188 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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| /linux/arch/powerpc/platforms/8xx/ |
| H A D | Kconfig | 155 This microcode relocates SMC1 and SMC2 parameter RAMs at
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| /linux/arch/xtensa/variants/dc233c/include/variant/ |
| H A D | core.h | 218 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
220 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
221 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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| /linux/arch/xtensa/variants/csp/include/variant/ |
| H A D | core.h | 284 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
286 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
287 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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| /linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | core.h | 285 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
287 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
288 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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| /linux/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| H A D | core.h | 242 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
244 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
245 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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| /linux/arch/xtensa/variants/de212/include/variant/ |
| H A D | core.h | 284 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
286 #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
287 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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| /linux/Documentation/arch/arm/stm32/ |
| H A D | stm32-dma-mdma-chaining.rst | 29 the system SRAM) for different peripheral. It can access external RAMs but
111 three fast access static internal RAMs of various size, used for data storage.
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| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,pru-rproc.yaml | 17 use the Data RAMs present within the PRU-ICSS for code execution.
|
| H A D | ti,omap-remoteproc.yaml | 110 any RAMs)
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| /linux/drivers/gpu/drm/armada/ |
| H A D | armada_plane.c | 248 /* Disable plane and power down most RAMs and FIFOs */ in armada_drm_primary_plane_atomic_disable()
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| /linux/arch/mips/include/asm/ |
| H A D | cpu-features.h | 595 * Some systems share FTLB RAMs between threads within a core (siblings in
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| /linux/drivers/net/ethernet/microchip/sparx5/ |
| H A D | sparx5_main.c | 971 /* Initialize Switchcore and internal RAMs */ in mchp_sparx5_probe()
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| /linux/drivers/net/ethernet/sun/ |
| H A D | cassini.h | 889 * checking all 17 RAMS.
915 RAMS */
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| /linux/drivers/soc/ti/ |
| H A D | knav_qmss_queue.c | 1150 * This gets a bit weird when other link rams are used. For example, in knav_get_link_ram()
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| /linux/drivers/crypto/inside-secure/ |
| H A D | safexcel.c | 240 /* Clear the cache RAMs */ in eip197_trc_cache_init()
|