| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | gddr5.c | 24 #include "ram.h"
35 nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts) in nvkm_gddr5_calc() argument
39 int rq = ram->freq < 1000000; /* XXX */ in nvkm_gddr5_calc()
41 xd = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr5_calc()
43 switch (ram->next->bios.ramcfg_ver) { in nvkm_gddr5_calc()
45 pd = ram->next->bios.ramcfg_11_01_80; in nvkm_gddr5_calc()
46 lf = ram->next->bios.ramcfg_11_01_40; in nvkm_gddr5_calc()
47 vh = ram->next->bios.ramcfg_11_02_10; in nvkm_gddr5_calc()
48 vr = ram->next->bios.ramcfg_11_02_04; in nvkm_gddr5_calc()
49 vo = ram->next->bios.ramcfg_11_06; in nvkm_gddr5_calc()
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| H A D | ramgk104.c | 25 #include "ram.h"
143 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); in gk104_ram_train() local
149 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { in gk104_ram_train()
150 if (ram->pmask & (1 << i)) in gk104_ram_train()
159 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); in r1373f4_init() local
160 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); in r1373f4_init()
161 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); in r1373f4_init()
162 const u32 runk0 = ram->fN1 << 16; in r1373f4_init()
163 const u32 runk1 = ram->fN1; in r1373f4_init()
165 if (ram->from == 2) { in r1373f4_init()
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| H A D | ram.c | 25 #include "ram.h"
33 struct nvkm_ram *ram; member
41 return nvkm_instobj_wrap(nvkm_vram(memory)->ram->fb->subdev.device, memory, pmemory); in nvkm_vram_kmap()
94 mutex_lock(&vram->ram->mutex); in nvkm_vram_dtor()
97 nvkm_mm_free(&vram->ram->vram, &node); in nvkm_vram_dtor()
99 mutex_unlock(&vram->ram->mutex); in nvkm_vram_dtor()
123 struct nvkm_ram *ram; in nvkm_ram_wrap() local
126 if (!device->fb || !(ram = device->fb->ram)) in nvkm_ram_wrap()
128 ram = device->fb->ram; in nvkm_ram_wrap()
134 vram->ram = ram; in nvkm_ram_wrap()
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| H A D | ramnv50.c | 25 #include "ram.h"
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_calc()
76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_calc()
86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
97 unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; in nv50_ram_timing_calc()
99 ram->base.next->bios.rammap_00_16_40) << 16 | in nv50_ram_timing_calc()
133 if (ram->base.type == NVKM_RAM_TYPE_DDR2) { in nv50_ram_timing_calc()
137 if (ram->base.type == NVKM_RAM_TYPE_GDDR3) { in nv50_ram_timing_calc()
151 nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_read() argument
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| H A D | ramfuc.h | 59 ramfuc_init(struct ramfuc *ram, struct nvkm_fb *fb) in ramfuc_init() argument
61 int ret = nvkm_memx_init(fb->subdev.device->pmu, &ram->memx); in ramfuc_init()
65 ram->sequence++; in ramfuc_init()
66 ram->fb = fb; in ramfuc_init()
71 ramfuc_exec(struct ramfuc *ram, bool exec) in ramfuc_exec() argument
74 if (ram->fb) { in ramfuc_exec()
75 ret = nvkm_memx_fini(&ram->memx, exec); in ramfuc_exec()
76 ram->fb = NULL; in ramfuc_exec()
82 ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg) in ramfuc_rd32() argument
84 struct nvkm_device *device = ram->fb->subdev.device; in ramfuc_rd32()
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| H A D | ramgt215.c | 26 #include "ram.h"
154 gt215_link_train(struct gt215_ram *ram) in gt215_link_train() argument
156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train()
157 struct gt215_ramfuc *fuc = &ram->fuc; in gt215_link_train()
158 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gt215_link_train()
194 ret = ram->base.func->calc(&ram->base, (u32) M0205T.freq * 1000); in gt215_link_train()
237 ram->base.func->calc(&ram->base, clk_current); in gt215_link_train()
246 ram_train_result(ram->base.fb, result, 64); in gt215_link_train()
272 gt215_link_train_init(struct gt215_ram *ram) in gt215_link_train_init() argument
280 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train_init()
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| H A D | gddr3.c | 25 #include "ram.h"
71 nvkm_gddr3_calc(struct nvkm_ram *ram) in nvkm_gddr3_calc() argument
75 switch (ram->next->bios.timing_ver) { in nvkm_gddr3_calc()
77 CWL = ram->next->bios.timing_10_CWL; in nvkm_gddr3_calc()
78 CL = ram->next->bios.timing_10_CL; in nvkm_gddr3_calc()
79 WR = ram->next->bios.timing_10_WR; in nvkm_gddr3_calc()
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
81 ODT = ram->next->bios.timing_10_ODT; in nvkm_gddr3_calc()
82 RON = ram->next->bios.ramcfg_RON; in nvkm_gddr3_calc()
85 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_gddr3_calc()
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| H A D | ramgf100.c | 25 #include "ram.h"
109 struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc); in gf100_ram_train() local
110 struct nvkm_fb *fb = ram->base.fb; in gf100_ram_train()
129 struct gf100_ram *ram = gf100_ram(base); in gf100_ram_calc() local
130 struct gf100_ramfuc *fuc = &ram->fuc; in gf100_ram_calc()
131 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gf100_ram_calc()
180 ret = ram_init(fuc, ram->base.fb); in gf100_ram_calc()
215 ret = gt215_pll_calc(subdev, &ram->refpll, ram->mempll.refclk, in gf100_ram_calc()
230 ret = gt215_pll_calc(subdev, &ram->mempll, freq, in gf100_ram_calc()
409 struct gf100_ram *ram = gf100_ram(base); in gf100_ram_prog() local
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| H A D | sddr3.c | 26 #include "ram.h"
70 nvkm_sddr3_calc(struct nvkm_ram *ram) in nvkm_sddr3_calc() argument
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
76 switch (ram->next->bios.timing_ver) { in nvkm_sddr3_calc()
78 if (ram->next->bios.timing_hdr < 0x17) { in nvkm_sddr3_calc()
82 CWL = ram->next->bios.timing_10_CWL; in nvkm_sddr3_calc()
83 CL = ram->next->bios.timing_10_CL; in nvkm_sddr3_calc()
84 WR = ram->next->bios.timing_10_WR; in nvkm_sddr3_calc()
85 ODT = ram->next->bios.timing_10_ODT; in nvkm_sddr3_calc()
88 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_sddr3_calc()
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| H A D | sddr2.c | 26 #include "ram.h"
61 nvkm_sddr2_calc(struct nvkm_ram *ram) in nvkm_sddr2_calc() argument
65 switch (ram->next->bios.timing_ver) { in nvkm_sddr2_calc()
67 CL = ram->next->bios.timing_10_CL; in nvkm_sddr2_calc()
68 WR = ram->next->bios.timing_10_WR; in nvkm_sddr2_calc()
69 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr2_calc()
70 ODT = ram->next->bios.timing_10_ODT & 3; in nvkm_sddr2_calc()
73 CL = (ram->next->bios.timing[1] & 0x0000001f); in nvkm_sddr2_calc()
74 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr2_calc()
80 if (ram->next->bios.timing_ver == 0x20 || in nvkm_sddr2_calc()
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| H A D | rammcp77.c | 25 #include "ram.h"
35 struct mcp77_ram *ram = mcp77_ram(base); in mcp77_ram_init() local
36 struct nvkm_device *device = ram->base.fb->subdev.device; in mcp77_ram_init()
37 u32 dniso = ((ram->base.size - (ram->poller_base + 0x00)) >> 5) - 1; in mcp77_ram_init()
38 u32 hostnb = ((ram->base.size - (ram->poller_base + 0x20)) >> 5) - 1; in mcp77_ram_init()
39 u32 flush = ((ram->base.size - (ram->poller_base + 0x40)) >> 5) - 1; in mcp77_ram_init()
66 struct mcp77_ram *ram; in mcp77_ram_new() local
69 if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) in mcp77_ram_new()
71 *pram = &ram->base; in mcp77_ram_new()
74 size, &ram->base); in mcp77_ram_new()
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| H A D | ramnv40.c | 36 struct nv40_ram *ram = nv40_ram(base); in nv40_ram_calc() local
37 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv40_ram_calc()
53 ram->ctrl = 0x80000000 | (log2P << 16); in nv40_ram_calc()
54 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20; in nv40_ram_calc()
56 ram->ctrl |= 0x00000100; in nv40_ram_calc()
57 ram->coef = (N1 << 8) | M1; in nv40_ram_calc()
59 ram->ctrl |= 0x40000000; in nv40_ram_calc()
60 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_ram_calc()
69 struct nv40_ram *ram = nv40_ram(base); in nv40_ram_prog() local
70 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv40_ram_prog()
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| H A D | r535.c | 23 #include "ram.h"
35 struct nvkm_ram *ram; in r535_fb_ram_new() local
38 if (!(ram = *pram = kzalloc(sizeof(*ram), GFP_KERNEL))) in r535_fb_ram_new()
41 ram->func = &r535_fb_ram; in r535_fb_ram_new()
42 ram->fb = fb; in r535_fb_ram_new()
43 ram->type = NVKM_RAM_TYPE_UNKNOWN; /*TODO: pull this from GSP. */ in r535_fb_ram_new()
44 ram->size = gsp->fb.size; in r535_fb_ram_new()
45 ram->stolen = false; in r535_fb_ram_new()
46 mutex_init(&ram->mutex); in r535_fb_ram_new()
49 ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL, in r535_fb_ram_new()
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| /linux/drivers/zorro/ |
| H A D | zorro.ids | 18 0000 Golem RAM Box 2MB [RAM Expansion]
22 1300 Warp Engine [Accelerator, SCSI Host Adapter and RAM Expansion]
24 0200 Megamix 2000 [RAM Expansion]
36 0a00 A590/A2052/A2058/A2091 [RAM Expansion]
37 2000 A560 [RAM Expansion]
40 5000 A2620 68020 [Accelerator and RAM Expansion]
41 5100 A2630 68030 [Accelerator and RAM Expansion]
51 0200 EXP8000 [RAM Expansion]
64 0100 AX2000 [RAM Expansion]
68 0000 StarBoard II [RAM Expansion]
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bus/ |
| H A D | hwsq.h | 61 hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev) in hwsq_init() argument
65 ret = nvkm_hwsq_init(subdev, &ram->hwsq); in hwsq_init()
69 ram->sequence++; in hwsq_init()
70 ram->subdev = subdev; in hwsq_init()
75 hwsq_exec(struct hwsq *ram, bool exec) in hwsq_exec() argument
78 if (ram->subdev) { in hwsq_exec()
79 ret = nvkm_hwsq_fini(&ram->hwsq, exec); in hwsq_exec()
80 ram->subdev = NULL; in hwsq_exec()
86 hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg) in hwsq_rd32() argument
88 struct nvkm_device *device = ram->subdev->device; in hwsq_rd32()
[all …]
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| /linux/Documentation/admin-guide/blockdev/ |
| H A D | ramdisk.rst | 2 Using the RAM disk block device with Linux
10 4) An Example of Creating a Compressed RAM Disk
16 The RAM disk driver is a way to use main system memory as a block device. It
22 The RAM disk dynamically grows as more space is required. It does this by using
23 RAM from the buffer cache. The driver marks the buffers it is using as dirty
26 The RAM disk supports up to 16 RAM disks by default, and can be reconfigured
27 to support an unlimited number of RAM disks (at your own risk). Just change
31 To use RAM disk support with your system, run './MAKEDEV ram' from the /dev
32 directory. RAM disks are all major number 1, and start with minor number 0
35 The new RAM disk also has the ability to load compressed RAM disk images,
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| /linux/include/linux/ |
| H A D | hp_sdc.h | 187 #define HP_SDC_CMD_READ_RAM 0x00 /* Load from i8042 RAM (autoinc) */
197 #define HP_SDC_CMD_READ_D0 0xf0 /* Load from i8042 RAM location 0x70 */
198 #define HP_SDC_CMD_READ_D1 0xf1 /* Load from i8042 RAM location 0x71 */
199 #define HP_SDC_CMD_READ_D2 0xf2 /* Load from i8042 RAM location 0x72 */
200 #define HP_SDC_CMD_READ_D3 0xf3 /* Load from i8042 RAM location 0x73 */
201 #define HP_SDC_CMD_READ_VT1 0xf4 /* Load from i8042 RAM location 0x74 */
202 #define HP_SDC_CMD_READ_VT2 0xf5 /* Load from i8042 RAM location 0x75 */
203 #define HP_SDC_CMD_READ_VT3 0xf6 /* Load from i8042 RAM location 0x76 */
204 #define HP_SDC_CMD_READ_VT4 0xf7 /* Load from i8042 RAM location 0x77 */
205 #define HP_SDC_CMD_READ_KBN 0xf8 /* Load from i8042 RAM location 0x78 */
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| /linux/arch/m68k/atari/ |
| H A D | stram.c | 2 * Functions for ST-RAM allocations
35 * The ST-RAM allocator allocates memory from a pool of reserved ST-RAM of
36 * configurable size, set aside on ST-RAM init.
37 * As long as this pool is not exhausted, allocation of real ST-RAM can be
41 /* set if kernel is in ST-RAM */
45 .name = "ST-RAM Pool"
73 * determine whether kernel code resides in ST-RAM in atari_stram_init()
74 * (then ST-RAM is the first memory block at virtual 0x0) in atari_stram_init()
84 /* Should never come here! (There is always ST-Ram!) */ in atari_stram_init()
85 panic("atari_stram_init: no ST-RAM found!"); in atari_stram_init()
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| /linux/Documentation/translations/zh_TW/arch/arm/ |
| H A D | Booting | 40 1、設置和初始化 RAM。
47 1、設置和初始化 RAM
53 引導裝載程序應該找到並初始化系統中所有內核用於保持系統變量數據的 RAM。
55 RAM，或可能使用對這個設備已知的 RAM 信息，還可能使用任何引導裝載程序
117 標籤列表應該保存在系統的 RAM 中。
120 建議放在 RAM 的頭 16KiB 中。
126 RAM 中，並用啓動數據初始化它。dtb 格式在文檔
132 dtb 必須置於內核自解壓不會覆蓋的內存區。建議將其放置於 RAM 的頭 16KiB
146 zImage 也可以被放在系統 RAM（任意位置）中被調用。注意：內核使用映像
147 基地址的前 16KB RAM 空間來保存頁表。建議將映像置於 RAM 的 32KB 處。
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| /linux/Documentation/translations/zh_CN/arch/arm/ |
| H A D | Booting | 40 1、设置和初始化 RAM。
47 1、设置和初始化 RAM
53 引导装载程序应该找到并初始化系统中所有内核用于保持系统变量数据的 RAM。
55 RAM，或可能使用对这个设备已知的 RAM 信息，还可能使用任何引导装载程序
117 标签列表应该保存在系统的 RAM 中。
120 建议放在 RAM 的头 16KiB 中。
126 RAM 中，并用启动数据初始化它。dtb 格式在文档
132 dtb 必须置于内核自解压不会覆盖的内存区。建议将其放置于 RAM 的头 16KiB
146 zImage 也可以被放在系统 RAM（任意位置）中被调用。注意：内核使用映像
147 基地址的前 16KB RAM 空间来保存页表。建议将映像置于 RAM 的 32KB 处。
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | davinci_emac.txt | 12 - ti,davinci-ctrl-ram-offset: offset to control module ram
13 - ti,davinci-ctrl-ram-size: size of control module ram
24 - ti,davinci-no-bd-ram: boolean, does EMAC have BD RAM?
35 ti,davinci-ctrl-ram-offset = <0>;
36 ti,davinci-ctrl-ram-size = <0x2000>;
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| /linux/include/soc/fsl/qe/ |
| H A D | immap_qe.h | 22 /* QE I-RAM */
24 __be32 iadd; /* I-RAM Address Register */
25 __be32 idata; /* I-RAM Data Register */
27 __be32 iready; /* I-RAM Ready Register */
69 __be16 cercr; /* QE RAM control register */
166 __be16 sirsr1_h; /* SI1 RAM shadow address register high */
167 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
168 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
169 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
170 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
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| /linux/Documentation/devicetree/bindings/net/can/ |
| H A D | bosch,m_can.yaml | 24 - description: message RAM
55 Message RAM configuration data.
56 Multiple M_CAN instances can share the same Message RAM
58 in Message RAM is also configurable, so this property is
59 telling driver how the shared or private Message RAM are
64 The 'offset' is an address offset of the Message RAM where
66 0x0 if you're using a private Message RAM. The remain cells
78 Please refer to 2.4.1 Message RAM Configuration in Bosch
82 - description: The 'offset' is an address offset of the Message RAM where
84 you're using a private Message RAM.
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| /linux/Documentation/arch/arm/ |
| H A D | booting.rst | 19 1. Setup and initialise the RAM.
27 1. Setup and initialise RAM
35 The boot loader is expected to find and initialise all RAM that the
38 to automatically locate and size all RAM, or it may use knowledge of
39 the RAM in the machine, or any other method the boot loader designer
120 The tagged list should be stored in system RAM.
124 it. The recommended placement is in the first 16KiB of RAM.
129 The boot loader must load a device tree image (dtb) into system ram
142 A safe location is just above the 128MiB boundary from start of RAM.
158 be loaded just above the 128MiB boundary from the start of RAM as
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| /linux/drivers/dax/ |
| H A D | Kconfig | 43 "System RAM" pool.
48 tristate "CXL DAX: direct access to CXL RAM regions"
52 CXL RAM regions are either mapped by platform-firmware
53 and published in the initial system-memory map as "System RAM", mapped
58 converted to "System RAM" via the dax_kmem facility.
65 tristate "KMEM DAX: map dax-devices as System-RAM"
71 differentiated memory as if it were System RAM. This allows
|